Lines Matching full:rcc
117 clocks = <&rcc TIM2_K>;
152 clocks = <&rcc TIM3_K>;
188 clocks = <&rcc TIM4_K>;
222 clocks = <&rcc TIM5_K>;
258 clocks = <&rcc TIM6_K>;
278 clocks = <&rcc TIM7_K>;
297 clocks = <&rcc LPTIM1_K>;
340 clocks = <&rcc SPI2_K>;
341 resets = <&rcc SPI2_R>;
365 clocks = <&rcc SPI3_K>;
366 resets = <&rcc SPI3_R>;
379 clocks = <&rcc SPDIF_K>;
392 clocks = <&rcc USART3_K>;
393 resets = <&rcc USART3_R>;
405 clocks = <&rcc UART4_K>;
406 resets = <&rcc UART4_R>;
418 clocks = <&rcc UART5_K>;
419 resets = <&rcc UART5_R>;
433 clocks = <&rcc I2C1_K>;
434 resets = <&rcc I2C1_R>;
451 clocks = <&rcc I2C2_K>;
452 resets = <&rcc I2C2_R>;
467 clocks = <&rcc UART7_K>;
468 resets = <&rcc UART7_R>;
480 clocks = <&rcc UART8_K>;
481 resets = <&rcc UART8_R>;
499 clocks = <&rcc TIM1_K>;
540 clocks = <&rcc TIM8_K>;
575 clocks = <&rcc USART6_K>;
576 resets = <&rcc USART6_R>;
599 clocks = <&rcc SPI1_K>;
600 resets = <&rcc SPI1_R>;
616 resets = <&rcc SAI1_R>;
623 clocks = <&rcc SAI1_K>;
633 clocks = <&rcc SAI1_K>;
647 resets = <&rcc SAI2_R>;
654 clocks = <&rcc SAI2_K>;
664 clocks = <&rcc SAI2_K>;
674 clocks = <&rcc DFSDM_K>;
712 clocks = <&rcc DMA1>;
713 resets = <&rcc DMA1_R>;
730 clocks = <&rcc DMA2>;
731 resets = <&rcc DMA2_R>;
740 clocks = <&rcc DMAMUX1>;
741 resets = <&rcc DMAMUX1_R>;
748 rcc: rcc@50000000 { label
749 compatible = "st,stm32mp13-rcc", "syscon";
867 clocks = <&rcc SYSCFG>;
874 clocks = <&rcc LPTIM4_K>;
895 clocks = <&rcc LPTIM5_K>;
916 clocks = <&rcc MDMA>;
925 clocks = <&rcc CRC1>;
932 clocks = <&usbphyc>, <&rcc USBH>;
933 resets = <&rcc USBH_R>;
941 clocks = <&usbphyc>, <&rcc USBH>;
942 resets = <&rcc USBH_R>;
951 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
1002 clocks = <&rcc ADC2>, <&rcc ADC2_K>;
1045 clocks = <&rcc USBO_K>;
1047 resets = <&rcc USBO_R>;
1064 clocks = <&rcc USART1_K>;
1065 resets = <&rcc USART1_R>;
1078 clocks = <&rcc USART2_K>;
1079 resets = <&rcc USART2_R>;
1104 clocks = <&rcc SPI4_K>;
1105 resets = <&rcc SPI4_R>;
1119 clocks = <&rcc SPI5_K>;
1120 resets = <&rcc SPI5_R>;
1136 clocks = <&rcc I2C3_K>;
1137 resets = <&rcc I2C3_R>;
1155 clocks = <&rcc I2C4_K>;
1156 resets = <&rcc I2C4_R>;
1174 clocks = <&rcc I2C5_K>;
1175 resets = <&rcc I2C5_R>;
1194 clocks = <&rcc TIM12_K>;
1219 clocks = <&rcc TIM13_K>;
1244 clocks = <&rcc TIM14_K>;
1269 clocks = <&rcc TIM15_K>;
1299 clocks = <&rcc TIM16_K>;
1327 clocks = <&rcc TIM17_K>;
1354 clocks = <&rcc LPTIM2_K>;
1389 clocks = <&rcc LPTIM3_K>;
1417 clocks = <&rcc HASH1>;
1418 resets = <&rcc HASH1_R>;
1428 clocks = <&rcc RNG1_K>;
1429 resets = <&rcc RNG1_R>;
1444 clocks = <&rcc FMC_K>;
1445 resets = <&rcc FMC_R>;
1478 clocks = <&rcc QSPI_K>;
1479 resets = <&rcc QSPI_R>;
1489 clocks = <&rcc SDMMC1_K>;
1491 resets = <&rcc SDMMC1_R>;
1504 clocks = <&rcc SDMMC2_K>;
1506 resets = <&rcc SDMMC2_R>;
1526 clocks = <&rcc ETH1MAC>,
1527 <&rcc ETH1TX>,
1528 <&rcc ETH1RX>,
1529 <&rcc ETH1STP>,
1530 <&rcc ETH1CK_K>;
1552 clocks = <&rcc USBPHY_K>;
1553 resets = <&rcc USBPHY_R>;
1589 clocks = <&rcc GPIOA>;
1601 clocks = <&rcc GPIOB>;
1613 clocks = <&rcc GPIOC>;
1625 clocks = <&rcc GPIOD>;
1637 clocks = <&rcc GPIOE>;
1649 clocks = <&rcc GPIOF>;
1661 clocks = <&rcc GPIOG>;
1673 clocks = <&rcc GPIOH>;
1685 clocks = <&rcc GPIOI>;