Lines Matching +full:0 +full:- +full:9 +full:a +full:- +full:d
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
9 /omit-if-no-ref/
10 adc1_pins_a: adc1-pins-0 {
12 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
16 /omit-if-no-ref/
17 adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
20 <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
24 /omit-if-no-ref/
25 adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 {
27 pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP2 */
32 /omit-if-no-ref/
33 dcmipp_pins_a: dcmi-0 {
36 <STM32_PINMUX('G', 9, AF13)>,/* DCMI_VSYNC */
38 <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */
39 <STM32_PINMUX('D', 0, AF13)>,/* DCMI_D1 */
42 <STM32_PINMUX('D', 11, AF14)>,/* DCMI_D4 */
43 <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
46 bias-disable;
50 /omit-if-no-ref/
51 dcmipp_sleep_pins_a: dcmi-sleep-0 {
54 <STM32_PINMUX('G', 9, ANALOG)>,/* DCMI_VSYNC */
56 <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */
57 <STM32_PINMUX('D', 0, ANALOG)>,/* DCMI_D1 */
60 <STM32_PINMUX('D', 11, ANALOG)>,/* DCMI_D4 */
61 <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
67 /omit-if-no-ref/
68 eth1_rgmii_pins_a: eth1-rgmii-0 {
76 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
78 bias-disable;
79 drive-push-pull;
80 slew-rate = <2>;
86 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
88 <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */
89 <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */
90 bias-disable;
94 /omit-if-no-ref/
95 eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
97 pinmux = <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
99 bias-disable;
100 drive-push-pull;
101 slew-rate = <2>;
113 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD1 */
115 <STM32_PINMUX('A', 7, ANALOG)>, /* ETH_RGMII_RX_CTL */
116 <STM32_PINMUX('D', 7, ANALOG)>; /* ETH_RGMII_RX_CLK */
120 /omit-if-no-ref/
121 eth1_rmii_pins_a: eth1-rmii-0 {
126 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
127 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
129 bias-disable;
130 drive-push-pull;
131 slew-rate = <1>;
138 bias-disable;
142 /omit-if-no-ref/
143 eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 {
148 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RMII_REF_CLK */
149 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
157 /omit-if-no-ref/
158 eth2_rgmii_pins_a: eth2-rgmii-0 {
168 bias-disable;
169 drive-push-pull;
170 slew-rate = <2>;
177 <STM32_PINMUX('A', 8, AF11)>, /* ETH_RGMII_RXD3 */
178 <STM32_PINMUX('A', 12, AF11)>, /* ETH_RGMII_RX_CTL */
180 bias-disable;
184 /omit-if-no-ref/
185 eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
189 bias-disable;
190 drive-push-pull;
191 slew-rate = <2>;
204 <STM32_PINMUX('A', 8, ANALOG)>, /* ETH_RGMII_RXD3 */
205 <STM32_PINMUX('A', 12, ANALOG)>, /* ETH_RGMII_RX_CTL */
210 /omit-if-no-ref/
211 eth2_rmii_pins_a: eth2-rmii-0 {
219 bias-disable;
220 drive-push-pull;
221 slew-rate = <1>;
227 <STM32_PINMUX('A', 12, AF11)>; /* ETH_RMII_CRS_DV */
228 bias-disable;
232 /omit-if-no-ref/
233 eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 {
243 <STM32_PINMUX('A', 12, ANALOG)>; /* ETH_RMII_CRS_DV */
247 /omit-if-no-ref/
248 goodix_pins_a: goodix-0 {
251 * via the pinctrl not the driver (a pull-down resistor
257 output-high;
258 bias-pull-up;
261 * Interrupt line must have a pull-down resistor
262 * in order to freeze the i2c address at 0x5D
266 bias-pull-down;
270 /omit-if-no-ref/
271 i2c1_pins_a: i2c1-0 {
273 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
275 bias-disable;
276 drive-open-drain;
277 slew-rate = <0>;
281 /omit-if-no-ref/
282 i2c1_sleep_pins_a: i2c1-sleep-0 {
284 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
289 /omit-if-no-ref/
290 i2c5_pins_a: i2c5-0 {
292 pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
294 bias-disable;
295 drive-open-drain;
296 slew-rate = <0>;
300 /omit-if-no-ref/
301 i2c5_sleep_pins_a: i2c5-sleep-0 {
303 pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
308 /omit-if-no-ref/
309 i2c5_pins_b: i2c5-1 {
311 pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
313 bias-disable;
314 drive-open-drain;
315 slew-rate = <0>;
319 /omit-if-no-ref/
320 i2c5_sleep_pins_b: i2c5-sleep-1 {
322 pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
327 /omit-if-no-ref/
328 ltdc_pins_a: ltdc-0 {
330 pinmux = <STM32_PINMUX('D', 9, AF13)>, /* LCD_CLK */
333 <STM32_PINMUX('H', 9, AF11)>, /* LCD_DE */
336 <STM32_PINMUX('D', 14, AF14)>, /* LCD_R4 */
339 <STM32_PINMUX('E', 9, AF14)>, /* LCD_R7 */
342 <STM32_PINMUX('D', 5, AF14)>, /* LCD_G4 */
343 <STM32_PINMUX('G', 0, AF14)>, /* LCD_G5 */
345 <STM32_PINMUX('A', 15, AF11)>, /* LCD_G7 */
346 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B2 */
349 <STM32_PINMUX('E', 0, AF14)>, /* LCD_B5 */
352 bias-disable;
353 drive-push-pull;
354 slew-rate = <0>;
358 /omit-if-no-ref/
359 ltdc_sleep_pins_a: ltdc-sleep-0 {
361 pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_CLK */
364 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_DE */
367 <STM32_PINMUX('D', 14, ANALOG)>, /* LCD_R4 */
370 <STM32_PINMUX('E', 9, ANALOG)>, /* LCD_R7 */
373 <STM32_PINMUX('D', 5, ANALOG)>, /* LCD_G4 */
374 <STM32_PINMUX('G', 0, ANALOG)>, /* LCD_G5 */
376 <STM32_PINMUX('A', 15, ANALOG)>, /* LCD_G7 */
377 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B2 */
380 <STM32_PINMUX('E', 0, ANALOG)>, /* LCD_B5 */
386 /omit-if-no-ref/
387 m_can1_pins_a: m-can1-0 {
390 slew-rate = <1>;
391 drive-push-pull;
392 bias-disable;
395 pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
396 bias-disable;
400 /omit-if-no-ref/
401 m_can1_sleep_pins_a: m_can1-sleep-0 {
404 <STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */
408 /omit-if-no-ref/
409 m_can2_pins_a: m-can2-0 {
411 pinmux = <STM32_PINMUX('G', 0, AF9)>; /* CAN2_TX */
412 slew-rate = <1>;
413 drive-push-pull;
414 bias-disable;
417 pinmux = <STM32_PINMUX('E', 0, AF9)>; /* CAN2_RX */
418 bias-disable;
422 /omit-if-no-ref/
423 m_can2_sleep_pins_a: m_can2-sleep-0 {
425 pinmux = <STM32_PINMUX('G', 0, ANALOG)>, /* CAN2_TX */
426 <STM32_PINMUX('E', 0, ANALOG)>; /* CAN2_RX */
430 /omit-if-no-ref/
431 mcp23017_pins_a: mcp23017-0 {
434 bias-pull-up;
438 /omit-if-no-ref/
439 pwm3_pins_a: pwm3-0 {
442 bias-pull-down;
443 drive-push-pull;
444 slew-rate = <0>;
448 /omit-if-no-ref/
449 pwm3_sleep_pins_a: pwm3-sleep-0 {
455 /omit-if-no-ref/
456 pwm4_pins_a: pwm4-0 {
458 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
459 bias-pull-down;
460 drive-push-pull;
461 slew-rate = <0>;
465 /omit-if-no-ref/
466 pwm4_sleep_pins_a: pwm4-sleep-0 {
468 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
472 /omit-if-no-ref/
473 pwm5_pins_a: pwm5-0 {
476 bias-pull-down;
477 drive-push-pull;
478 slew-rate = <0>;
482 /omit-if-no-ref/
483 pwm5_sleep_pins_a: pwm5-sleep-0 {
489 /omit-if-no-ref/
490 pwm8_pins_a: pwm8-0 {
493 bias-pull-down;
494 drive-push-pull;
495 slew-rate = <0>;
499 /omit-if-no-ref/
500 pwm8_sleep_pins_a: pwm8-sleep-0 {
506 /omit-if-no-ref/
507 pwm13_pins_a: pwm13-0 {
509 pinmux = <STM32_PINMUX('A', 6, AF9)>; /* TIM13_CH1 */
510 bias-pull-down;
511 drive-push-pull;
512 slew-rate = <0>;
516 /omit-if-no-ref/
517 pwm13_sleep_pins_a: pwm13-sleep-0 {
519 pinmux = <STM32_PINMUX('A', 6, ANALOG)>; /* TIM13_CH1 */
523 /omit-if-no-ref/
524 pwm14_pins_a: pwm14-0 {
526 pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
527 bias-pull-down;
528 drive-push-pull;
529 slew-rate = <0>;
533 /omit-if-no-ref/
534 pwm14_sleep_pins_a: pwm14-sleep-0 {
536 pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */
540 /omit-if-no-ref/
541 qspi_clk_pins_a: qspi-clk-0 {
544 bias-disable;
545 drive-push-pull;
546 slew-rate = <3>;
550 /omit-if-no-ref/
551 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
557 /omit-if-no-ref/
558 qspi_bk1_pins_a: qspi-bk1-0 {
561 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
562 <STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2 */
564 bias-disable;
565 drive-push-pull;
566 slew-rate = <1>;
570 /omit-if-no-ref/
571 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
574 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
575 <STM32_PINMUX('D', 11, ANALOG)>, /* QSPI_BK1_IO2 */
580 /omit-if-no-ref/
581 qspi_cs1_pins_a: qspi-cs1-0 {
584 bias-pull-up;
585 drive-push-pull;
586 slew-rate = <1>;
590 /omit-if-no-ref/
591 qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
597 /omit-if-no-ref/
598 sai1a_pins_a: sai1a-0 {
600 pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */
601 <STM32_PINMUX('D', 6, AF6)>, /* SAI1_SD_A */
603 slew-rate = <0>;
604 drive-push-pull;
605 bias-disable;
609 /omit-if-no-ref/
610 sai1a_sleep_pins_a: sai1a-sleep-0 {
612 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */
613 <STM32_PINMUX('D', 6, ANALOG)>, /* SAI1_SD_A */
618 /omit-if-no-ref/
619 sai1b_pins_a: sai1b-0 {
621 pinmux = <STM32_PINMUX('A', 0, AF6)>; /* SAI1_SD_B */
622 bias-disable;
626 /omit-if-no-ref/
627 sai1b_sleep_pins_a: sai1b-sleep-0 {
629 pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* SAI1_SD_B */
633 /omit-if-no-ref/
634 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
637 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
640 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
641 slew-rate = <1>;
642 drive-push-pull;
643 bias-disable;
647 /omit-if-no-ref/
648 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
651 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
654 slew-rate = <1>;
655 drive-push-pull;
656 bias-disable;
659 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
660 slew-rate = <1>;
661 drive-open-drain;
662 bias-disable;
666 /omit-if-no-ref/
667 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
670 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
674 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
678 /omit-if-no-ref/
679 sdmmc1_clk_pins_a: sdmmc1-clk-0 {
682 slew-rate = <1>;
683 drive-push-pull;
684 bias-disable;
688 /omit-if-no-ref/
689 sdmmc2_b4_pins_a: sdmmc2-b4-0 {
696 slew-rate = <1>;
697 drive-push-pull;
698 bias-pull-up;
702 /omit-if-no-ref/
703 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
709 slew-rate = <1>;
710 drive-push-pull;
711 bias-pull-up;
715 slew-rate = <1>;
716 drive-open-drain;
717 bias-pull-up;
721 /omit-if-no-ref/
722 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
733 /omit-if-no-ref/
734 sdmmc2_clk_pins_a: sdmmc2-clk-0 {
737 slew-rate = <1>;
738 drive-push-pull;
739 bias-pull-up;
743 /omit-if-no-ref/
744 sdmmc2_d47_pins_a: sdmmc2-d47-0 {
746 pinmux = <STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */
747 <STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */
750 slew-rate = <1>;
751 drive-push-pull;
752 bias-pull-up;
756 /omit-if-no-ref/
757 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
759 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */
760 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */
766 /omit-if-no-ref/
767 spi2_pins_a: spi2-0 {
771 bias-disable;
772 drive-push-pull;
773 slew-rate = <1>;
778 bias-disable;
782 /omit-if-no-ref/
783 spi2_sleep_pins_a: spi2-sleep-0 {
791 /omit-if-no-ref/
792 spi3_pins_a: spi3-0 {
796 bias-disable;
797 drive-push-pull;
798 slew-rate = <1>;
802 pinmux = <STM32_PINMUX('D', 4, AF5)>; /* SPI3_MISO */
803 bias-disable;
807 /omit-if-no-ref/
808 spi3_sleep_pins_a: spi3-sleep-0 {
811 <STM32_PINMUX('D', 4, ANALOG)>, /* SPI3_MISO */
816 /omit-if-no-ref/
817 spi5_pins_a: spi5-0 {
821 bias-disable;
822 drive-push-pull;
823 slew-rate = <1>;
827 pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */
828 bias-disable;
832 /omit-if-no-ref/
833 spi5_sleep_pins_a: spi5-sleep-0 {
836 <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */
841 /omit-if-no-ref/
842 stm32g0_intn_pins_a: stm32g0-intn-0 {
845 bias-pull-up;
849 /omit-if-no-ref/
850 uart4_pins_a: uart4-0 {
852 pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
853 bias-disable;
854 drive-push-pull;
855 slew-rate = <0>;
858 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
859 bias-disable;
863 /omit-if-no-ref/
864 uart4_idle_pins_a: uart4-idle-0 {
866 pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
869 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
870 bias-disable;
874 /omit-if-no-ref/
875 uart4_sleep_pins_a: uart4-sleep-0 {
877 pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
878 <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
882 /omit-if-no-ref/
883 uart4_pins_b: uart4-1 {
885 pinmux = <STM32_PINMUX('A', 9, AF8)>; /* UART4_TX */
886 bias-disable;
887 drive-push-pull;
888 slew-rate = <0>;
891 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
892 bias-pull-up;
896 /omit-if-no-ref/
897 uart4_idle_pins_b: uart4-idle-1 {
899 pinmux = <STM32_PINMUX('A', 9, ANALOG)>; /* UART4_TX */
902 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
903 bias-pull-up;
907 /omit-if-no-ref/
908 uart4_sleep_pins_b: uart4-sleep-1 {
910 pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* UART4_TX */
911 <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
915 /omit-if-no-ref/
916 uart7_pins_a: uart7-0 {
920 bias-disable;
921 drive-push-pull;
922 slew-rate = <0>;
927 bias-disable;
931 /omit-if-no-ref/
932 uart7_idle_pins_a: uart7-idle-0 {
939 bias-disable;
940 drive-push-pull;
941 slew-rate = <0>;
945 bias-disable;
949 /omit-if-no-ref/
950 uart7_sleep_pins_a: uart7-sleep-0 {
959 /omit-if-no-ref/
960 uart8_pins_a: uart8-0 {
963 bias-disable;
964 drive-push-pull;
965 slew-rate = <0>;
968 pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
969 bias-pull-up;
973 /omit-if-no-ref/
974 uart8_idle_pins_a: uart8-idle-0 {
979 pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
980 bias-pull-up;
984 /omit-if-no-ref/
985 uart8_sleep_pins_a: uart8-sleep-0 {
988 <STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
992 /omit-if-no-ref/
993 usart1_pins_a: usart1-0 {
995 pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
997 bias-disable;
998 drive-push-pull;
999 slew-rate = <0>;
1002 pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
1003 <STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
1004 bias-pull-up;
1008 /omit-if-no-ref/
1009 usart1_idle_pins_a: usart1-idle-0 {
1011 pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
1012 <STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
1016 bias-disable;
1017 drive-push-pull;
1018 slew-rate = <0>;
1021 pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
1022 bias-pull-up;
1026 /omit-if-no-ref/
1027 usart1_sleep_pins_a: usart1-sleep-0 {
1029 pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
1031 <STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
1032 <STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
1036 /omit-if-no-ref/
1037 usart1_pins_b: usart1-1 {
1039 pinmux = <STM32_PINMUX('C', 0, AF7)>; /* USART1_TX */
1040 bias-disable;
1041 drive-push-pull;
1042 slew-rate = <0>;
1045 pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
1046 bias-pull-up;
1050 /omit-if-no-ref/
1051 usart1_idle_pins_b: usart1-idle-1 {
1053 pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* USART1_TX */
1056 pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
1057 bias-pull-up;
1061 /omit-if-no-ref/
1062 usart1_sleep_pins_b: usart1-sleep-1 {
1064 pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
1065 <STM32_PINMUX('D', 14, ANALOG)>; /* USART1_RX */
1069 /omit-if-no-ref/
1070 usart2_pins_a: usart2-0 {
1073 <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
1074 bias-disable;
1075 drive-push-pull;
1076 slew-rate = <0>;
1079 pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
1081 bias-disable;
1085 /omit-if-no-ref/
1086 usart2_idle_pins_a: usart2-idle-0 {
1092 pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
1093 bias-disable;
1094 drive-push-pull;
1095 slew-rate = <0>;
1098 pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
1099 bias-disable;
1103 /omit-if-no-ref/
1104 usart2_sleep_pins_a: usart2-sleep-0 {
1107 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
1108 <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
1113 /omit-if-no-ref/
1114 usart2_pins_b: usart2-1 {
1117 <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
1118 bias-disable;
1119 drive-push-pull;
1120 slew-rate = <0>;
1123 pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
1125 bias-disable;
1129 /omit-if-no-ref/
1130 usart2_idle_pins_b: usart2-idle-1 {
1136 pinmux = <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
1137 bias-disable;
1138 drive-push-pull;
1139 slew-rate = <0>;
1142 pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
1143 bias-disable;
1147 /omit-if-no-ref/
1148 usart2_sleep_pins_b: usart2-sleep-1 {
1151 <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
1152 <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */