dts/st/stm32f746.dtsi

45 #include <dt-bindings/mfd/stm32f7-rcc.h>
83 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
105 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
127 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
149 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
171 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
187 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
203 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
223 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
237 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
251 			clocks = <&rcc 1 CLK_RTC>;
252 			assigned-clocks = <&rcc 1 CLK_RTC>;
253 			assigned-clock-parents = <&rcc 1 CLK_LSE>;
266 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>;
276 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>;
284 			clocks = <&rcc 1 CLK_USART2>;
292 			clocks = <&rcc 1 CLK_USART3>;
300 			clocks = <&rcc 1 CLK_UART4>;
308 			clocks = <&rcc 1 CLK_UART5>;
317 			resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
318 			clocks = <&rcc 1 CLK_I2C1>;
329 			resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
330 			clocks = <&rcc 1 CLK_I2C2>;
341 			resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
342 			clocks = <&rcc 1 CLK_I2C3>;
353 			resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
354 			clocks = <&rcc 1 CLK_I2C4>;
365 			resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
366 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
375 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
383 			resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
384 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
394 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
403 			clocks = <&rcc 1 CLK_UART7>;
411 			clocks = <&rcc 1 CLK_UART8>;
420 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
442 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
463 			clocks = <&rcc 1 CLK_USART1>;
471 			clocks = <&rcc 1 CLK_USART6>;
479 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
490 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
503 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>;
513 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>;
520 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SYSCFG)>;
536 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
556 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
570 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
587 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>;
597 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>;
605 			resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
606 			clocks = <&rcc 1 CLK_LCD>;
619 			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
623 		rcc: rcc@40023800 {  label
626 			compatible = "st,stm32f746-rcc", "st,stm32-rcc";
630 			assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
645 			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
661 			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
671 			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
683 			clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
691 	clocks = <&rcc 1 0>;