dts/st/stm32f429.dtsi

50 #include <dt-bindings/mfd/stm32f4-rcc.h>
101 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
123 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
145 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
167 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
189 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
205 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
221 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
241 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
255 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
269 			clocks = <&rcc 1 CLK_RTC>;
270 			assigned-clocks = <&rcc 1 CLK_RTC>;
271 			assigned-clock-parents = <&rcc 1 CLK_LSE>;
292 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
302 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
310 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
318 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
329 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
337 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
346 			resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
347 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
358 			resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
359 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
370 			resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
371 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
380 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
388 			resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
389 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
398 			resets = <&rcc STM32F4_APB1_RESET(DAC)>;
399 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
424 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
432 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
441 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
463 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
484 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
495 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
503 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
515 				clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
527 				clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
539 				clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
552 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
565 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
575 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
582 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(SYSCFG)>;
598 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
618 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
632 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
649 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
662 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
675 			resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
676 			clocks = <&rcc 1 CLK_LCD>;
684 			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
688 		rcc: rcc@40023800 {  label
691 			compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
695 			assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
710 			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
725 			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
737 			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
738 					<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
739 					<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
750 			resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
751 			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
760 			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
769 			clocks = <&rcc 0 39>;
778 			resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
779 			clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
791 			clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
798 	clocks = <&rcc 1 SYSTICK>;