Lines Matching +full:0 +full:x6000000
17 #phy-cells = <0>;
18 st,syscfg = <&syscfg_core 0xf8 0xf4>;
28 #phy-cells = <0>;
29 st,syscfg = <&syscfg_core 0xfc 0xf4>;
40 reg = <0x9a03c00 0x100>;
55 reg = <0x9a03e00 0x100>;
58 pinctrl-0 = <&pinctrl_usb0>;
72 reg = <0x9a83c00 0x100>;
87 reg = <0x9a83e00 0x100>;
90 pinctrl-0 = <&pinctrl_usb1>;
102 sti-display-subsystem@0 {
107 reg = <0 0>;
108 assigned-clocks = <&clk_s_d2_quadfs 0>,
110 <&clk_s_c0_pll1 0>,
120 assigned-clock-parents = <0>,
121 <0>,
122 <0>,
123 <&clk_s_c0_pll1 0>,
124 <&clk_s_c0_pll1 0>,
125 <&clk_s_d2_quadfs 0>,
127 <&clk_s_d2_quadfs 0>,
128 <&clk_s_d2_quadfs 0>,
129 <&clk_s_d2_quadfs 0>,
130 <&clk_s_d2_quadfs 0>;
134 <0>,
142 reg = <0x9d11000 0x1000>;
163 <&clk_s_d2_quadfs 0>,
174 reg = <0x8d08000 0x1000>;
187 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
189 <&clk_s_d2_quadfs 0>,
190 <&clk_s_d0_quadfs 0>,
191 <&clk_s_d2_quadfs 0>,
192 <&clk_s_d2_quadfs 0>;
197 reg = <0x8d04000 0x1000>;
199 #sound-dai-cells = <0>;
213 <&clk_s_d2_quadfs 0>,
225 reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
233 <&clk_s_d2_quadfs 0>,
239 reg = <0x9C00000 0x100000>;
251 reg = <0x9f10000 0x1000>;
259 reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
269 reg = <0x91a0000 0x28>;
273 #thermal-sensor-cells = <0>;
278 reg = <0x94a087c 0x64>;
284 pinctrl-0 = <&pinctrl_cec0_default>;