dts/st/spear320.dtsi

1 // SPDX-License-Identifier: GPL-2.0-or-later
12 		#address-cells = <1>;
13 		#size-cells = <1>;
14 		compatible = "simple-bus";
19 			compatible = "st,spear320-pinmux";
21 			#gpio-range-cells = <3>;
28 			interrupt-parent = <&shirq>;
33 			compatible = "st,spear600-fsmc-nand";
34 			#address-cells = <1>;
35 			#size-cells = <1>;
37 			       0x50000000 0x0010	/* NAND Base DATA */
38 			       0x50020000 0x0010	/* NAND Base ADDR */
39 			       0x50010000 0x0010>;	/* NAND Base CMD */
40 			reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
45 			compatible = "st,sdhci-spear";
48 			interrupt-parent = <&shirq>;
52 		shirq: interrupt-controller@b3000000 {
53 			compatible = "st,spear320-shirq";
56 			#interrupt-cells = <1>;
57 			interrupt-controller;
64 			interrupt-parent = <&shirq>;
65 			#address-cells = <1>;
66 			#size-cells = <0>;
74 			interrupt-parent = <&shirq>;
75 			#address-cells = <1>;
76 			#size-cells = <0>;
81 			compatible = "st,spear-pwm";
83 			#pwm-cells = <2>;
88 			#address-cells = <1>;
89 			#size-cells = <1>;
90 			compatible = "simple-bus";
95 				#address-cells = <1>;
96 				#size-cells = <0>;
97 				compatible = "snps,designware-i2c";
100 				interrupt-parent = <&shirq>;
108 				interrupt-parent = <&shirq>;
116 				interrupt-parent = <&shirq>;
121 				compatible = "st,spear-plgpio";
124 				#interrupt-cells = <1>;
125 				interrupt-controller;
126 				gpio-controller;
127 				#gpio-cells = <2>;
128 				gpio-ranges = <&pinmux 0 0 102>;
131 				st-plgpio,ngpio = <102>;
132 				st-plgpio,enb-reg = <0x24>;
133 				st-plgpio,wdata-reg = <0x34>;
134 				st-plgpio,dir-reg = <0x44>;
135 				st-plgpio,ie-reg = <0x64>;
136 				st-plgpio,rdata-reg = <0x54>;
137 				st-plgpio,mis-reg = <0x84>;
138 				st-plgpio,eit-reg = <0x94>;