dts/samsung/exynos5420-cpus.dtsi

1 // SPDX-License-Identifier: GPL-2.0
3  * Samsung Exynos5420 SoC cpu device tree source
9  * boards: CPU[0123] being the A15.
11  * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
14  * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16  * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17  * from the LITTLE: Cortex-A7.
22 		#address-cells = <1>;
23 		#size-cells = <0>;
25 		cpu-map {
28 					cpu = <&cpu0>;
31 					cpu = <&cpu1>;
34 					cpu = <&cpu2>;
37 					cpu = <&cpu3>;
43 					cpu = <&cpu4>;
46 					cpu = <&cpu5>;
49 					cpu = <&cpu6>;
52 					cpu = <&cpu7>;
57 		cpu0: cpu@0 {
58 			device_type = "cpu";
59 			compatible = "arm,cortex-a15";
62 			clock-frequency = <1800000000>;
63 			cci-control-port = <&cci_control1>;
64 			operating-points-v2 = <&cluster_a15_opp_table>;
65 			#cooling-cells = <2>; /* min followed by max */
66 			capacity-dmips-mhz = <1024>;
69 		cpu1: cpu@1 {
70 			device_type = "cpu";
71 			compatible = "arm,cortex-a15";
74 			clock-frequency = <1800000000>;
75 			cci-control-port = <&cci_control1>;
76 			operating-points-v2 = <&cluster_a15_opp_table>;
77 			#cooling-cells = <2>; /* min followed by max */
78 			capacity-dmips-mhz = <1024>;
81 		cpu2: cpu@2 {
82 			device_type = "cpu";
83 			compatible = "arm,cortex-a15";
86 			clock-frequency = <1800000000>;
87 			cci-control-port = <&cci_control1>;
88 			operating-points-v2 = <&cluster_a15_opp_table>;
89 			#cooling-cells = <2>; /* min followed by max */
90 			capacity-dmips-mhz = <1024>;
93 		cpu3: cpu@3 {
94 			device_type = "cpu";
95 			compatible = "arm,cortex-a15";
98 			clock-frequency = <1800000000>;
99 			cci-control-port = <&cci_control1>;
100 			operating-points-v2 = <&cluster_a15_opp_table>;
101 			#cooling-cells = <2>; /* min followed by max */
102 			capacity-dmips-mhz = <1024>;
105 		cpu4: cpu@100 {
106 			device_type = "cpu";
107 			compatible = "arm,cortex-a7";
110 			clock-frequency = <1000000000>;
111 			cci-control-port = <&cci_control0>;
112 			operating-points-v2 = <&cluster_a7_opp_table>;
113 			#cooling-cells = <2>; /* min followed by max */
114 			capacity-dmips-mhz = <539>;
117 		cpu5: cpu@101 {
118 			device_type = "cpu";
119 			compatible = "arm,cortex-a7";
122 			clock-frequency = <1000000000>;
123 			cci-control-port = <&cci_control0>;
124 			operating-points-v2 = <&cluster_a7_opp_table>;
125 			#cooling-cells = <2>; /* min followed by max */
126 			capacity-dmips-mhz = <539>;
129 		cpu6: cpu@102 {
130 			device_type = "cpu";
131 			compatible = "arm,cortex-a7";
134 			clock-frequency = <1000000000>;
135 			cci-control-port = <&cci_control0>;
136 			operating-points-v2 = <&cluster_a7_opp_table>;
137 			#cooling-cells = <2>; /* min followed by max */
138 			capacity-dmips-mhz = <539>;
141 		cpu7: cpu@103 {
142 			device_type = "cpu";
143 			compatible = "arm,cortex-a7";
146 			clock-frequency = <1000000000>;
147 			cci-control-port = <&cci_control0>;
148 			operating-points-v2 = <&cluster_a7_opp_table>;
149 			#cooling-cells = <2>; /* min followed by max */
150 			capacity-dmips-mhz = <539>;
156 	interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
161 	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;