Lines Matching +full:s3c6410 +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
19 #include <dt-bindings/clock/exynos4.h>
20 #include <dt-bindings/clock/exynos-audss-clk.h>
21 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/interrupt-controller/irq.h>
25 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <1>;
55 compatible = "arm,cortex-a9-pmu";
56 interrupt-parent = <&combiner>;
61 compatible = "simple-bus";
62 #address-cells = <1>;
63 #size-cells = <1>;
66 clock_audss: clock-controller@3810000 {
67 compatible = "samsung,exynos4210-audss-clock";
69 #clock-cells = <1>;
70 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
71 <&clock CLK_SCLK_AUDIO0>,
72 <&clock CLK_SCLK_AUDIO0>;
73 clock-names = "pll_ref", "pll_in", "sclk_audio",
78 compatible = "samsung,s5pv210-i2s";
83 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
84 #clock-cells = <1>;
85 clock-output-names = "i2s_cdclk0";
87 dma-names = "tx", "rx", "tx-sec";
88 samsung,idma-addr = <0x03000000>;
89 #sound-dai-cells = <1>;
94 compatible = "samsung,exynos4210-chipid";
98 scu: snoop-control-unit@10500000 {
99 compatible = "arm,cortex-a9-scu";
103 memory-controller@12570000 {
104 compatible = "samsung,exynos4210-srom";
108 pd_mfc: power-domain@10023c40 {
109 compatible = "samsung,exynos4210-pd";
111 #power-domain-cells = <0>;
115 pd_g3d: power-domain@10023c60 {
116 compatible = "samsung,exynos4210-pd";
118 #power-domain-cells = <0>;
122 pd_lcd0: power-domain@10023c80 {
123 compatible = "samsung,exynos4210-pd";
125 #power-domain-cells = <0>;
129 pd_tv: power-domain@10023c20 {
130 compatible = "samsung,exynos4210-pd";
132 #power-domain-cells = <0>;
133 power-domains = <&pd_lcd0>;
137 pd_cam: power-domain@10023c00 {
138 compatible = "samsung,exynos4210-pd";
140 #power-domain-cells = <0>;
144 pd_gps: power-domain@10023ce0 {
145 compatible = "samsung,exynos4210-pd";
147 #power-domain-cells = <0>;
151 pd_gps_alive: power-domain@10023d00 {
152 compatible = "samsung,exynos4210-pd";
154 #power-domain-cells = <0>;
158 gic: interrupt-controller@10490000 {
159 compatible = "arm,cortex-a9-gic";
160 #interrupt-cells = <3>;
161 interrupt-controller;
165 combiner: interrupt-controller@10440000 {
166 compatible = "samsung,exynos4210-combiner";
167 #interrupt-cells = <2>;
168 interrupt-controller;
173 compatible = "samsung,exynos4-sysreg", "syscon";
177 pmu_system_controller: system-controller@10020000 {
178 compatible = "samsung,exynos4210-pmu", "simple-mfd", "syscon";
180 interrupt-controller;
181 #interrupt-cells = <3>;
182 interrupt-parent = <&gic>;
184 mipi_phy: mipi-phy {
185 compatible = "samsung,s5pv210-mipi-video-phy";
186 #phy-cells = <1>;
191 compatible = "samsung,exynos4210-mipi-dsi";
194 power-domains = <&pd_lcd0>;
196 phy-names = "dsim";
197 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
198 clock-names = "bus_clk", "sclk_mipi";
200 #address-cells = <1>;
201 #size-cells = <0>;
208 #address-cells = <1>;
209 #size-cells = <1>;
210 #clock-cells = <1>;
211 clock-output-names = "cam_a_clkout", "cam_b_clkout";
214 compatible = "samsung,exynos4210-fimc";
217 clocks = <&clock CLK_FIMC0>,
218 <&clock CLK_SCLK_FIMC0>;
219 clock-names = "fimc", "sclk_fimc";
220 power-domains = <&pd_cam>;
227 compatible = "samsung,exynos4210-fimc";
230 clocks = <&clock CLK_FIMC1>,
231 <&clock CLK_SCLK_FIMC1>;
232 clock-names = "fimc", "sclk_fimc";
233 power-domains = <&pd_cam>;
240 compatible = "samsung,exynos4210-fimc";
243 clocks = <&clock CLK_FIMC2>,
244 <&clock CLK_SCLK_FIMC2>;
245 clock-names = "fimc", "sclk_fimc";
246 power-domains = <&pd_cam>;
253 compatible = "samsung,exynos4210-fimc";
256 clocks = <&clock CLK_FIMC3>,
257 <&clock CLK_SCLK_FIMC3>;
258 clock-names = "fimc", "sclk_fimc";
259 power-domains = <&pd_cam>;
266 compatible = "samsung,exynos4210-csis";
269 clocks = <&clock CLK_CSIS0>,
270 <&clock CLK_SCLK_CSIS0>;
271 clock-names = "csis", "sclk_csis";
272 bus-width = <4>;
273 power-domains = <&pd_cam>;
275 phy-names = "csis";
277 #address-cells = <1>;
278 #size-cells = <0>;
282 compatible = "samsung,exynos4210-csis";
285 clocks = <&clock CLK_CSIS1>,
286 <&clock CLK_SCLK_CSIS1>;
287 clock-names = "csis", "sclk_csis";
288 bus-width = <2>;
289 power-domains = <&pd_cam>;
291 phy-names = "csis";
293 #address-cells = <1>;
294 #size-cells = <0>;
299 compatible = "samsung,s3c6410-rtc";
301 interrupt-parent = <&pmu_system_controller>;
304 clocks = <&clock CLK_RTC>;
305 clock-names = "rtc";
310 compatible = "samsung,s5pv210-keypad";
313 clocks = <&clock CLK_KEYIF>;
314 clock-names = "keypad";
319 compatible = "samsung,exynos4210-sdhci";
322 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
323 clock-names = "hsmmc", "mmc_busclk.2";
328 compatible = "samsung,exynos4210-sdhci";
331 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
332 clock-names = "hsmmc", "mmc_busclk.2";
337 compatible = "samsung,exynos4210-sdhci";
340 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
341 clock-names = "hsmmc", "mmc_busclk.2";
346 compatible = "samsung,exynos4210-sdhci";
349 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
350 clock-names = "hsmmc", "mmc_busclk.2";
354 exynos_usbphy: usb-phy@125b0000 {
355 compatible = "samsung,exynos4210-usb2-phy";
357 samsung,pmureg-phandle = <&pmu_system_controller>;
358 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
359 clock-names = "phy", "ref";
360 #phy-cells = <1>;
365 compatible = "samsung,s3c6400-hsotg";
368 clocks = <&clock CLK_USB_DEVICE>;
369 clock-names = "otg";
371 phy-names = "usb2-phy";
376 compatible = "samsung,exynos4210-ehci";
379 clocks = <&clock CLK_USB_HOST>;
380 clock-names = "usbhost";
383 phy-names = "host", "hsic0", "hsic1";
387 compatible = "samsung,exynos4210-ohci";
390 clocks = <&clock CLK_USB_HOST>;
391 clock-names = "usbhost";
394 phy-names = "host";
398 compatible = "samsung,exynos4210-mali", "arm,mali-400";
401 * CLK_G3D is not actually bus clock but a IP-level clock.
402 * The bus clock is not described in hardware manual.
404 clocks = <&clock CLK_G3D>,
405 <&clock CLK_SCLK_G3D>;
406 clock-names = "bus", "core";
407 power-domains = <&pd_g3d>;
412 compatible = "samsung,s3c6410-i2s";
414 clocks = <&clock CLK_I2S1>;
415 clock-names = "iis";
416 #clock-cells = <1>;
417 clock-output-names = "i2s_cdclk1";
419 dma-names = "tx", "rx";
420 #sound-dai-cells = <1>;
425 compatible = "samsung,s3c6410-i2s";
427 clocks = <&clock CLK_I2S2>;
428 clock-names = "iis";
429 #clock-cells = <1>;
430 clock-output-names = "i2s_cdclk2";
432 dma-names = "tx", "rx";
433 #sound-dai-cells = <1>;
438 compatible = "samsung,mfc-v5";
441 power-domains = <&pd_mfc>;
442 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
443 clock-names = "mfc", "sclk_mfc";
445 iommu-names = "left", "right";
449 compatible = "samsung,exynos4210-uart";
452 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
453 clock-names = "uart", "clk_uart_baud0";
455 dma-names = "rx", "tx";
460 compatible = "samsung,exynos4210-uart";
463 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
464 clock-names = "uart", "clk_uart_baud0";
466 dma-names = "rx", "tx";
471 compatible = "samsung,exynos4210-uart";
474 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
475 clock-names = "uart", "clk_uart_baud0";
477 dma-names = "rx", "tx";
482 compatible = "samsung,exynos4210-uart";
485 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
486 clock-names = "uart", "clk_uart_baud0";
488 dma-names = "rx", "tx";
493 #address-cells = <1>;
494 #size-cells = <0>;
495 compatible = "samsung,s3c2440-i2c";
498 clocks = <&clock CLK_I2C0>;
499 clock-names = "i2c";
500 pinctrl-names = "default";
501 pinctrl-0 = <&i2c0_bus>;
506 #address-cells = <1>;
507 #size-cells = <0>;
508 compatible = "samsung,s3c2440-i2c";
511 clocks = <&clock CLK_I2C1>;
512 clock-names = "i2c";
513 pinctrl-names = "default";
514 pinctrl-0 = <&i2c1_bus>;
519 #address-cells = <1>;
520 #size-cells = <0>;
521 compatible = "samsung,s3c2440-i2c";
524 clocks = <&clock CLK_I2C2>;
525 clock-names = "i2c";
526 pinctrl-names = "default";
527 pinctrl-0 = <&i2c2_bus>;
532 #address-cells = <1>;
533 #size-cells = <0>;
534 compatible = "samsung,s3c2440-i2c";
537 clocks = <&clock CLK_I2C3>;
538 clock-names = "i2c";
539 pinctrl-names = "default";
540 pinctrl-0 = <&i2c3_bus>;
545 #address-cells = <1>;
546 #size-cells = <0>;
547 compatible = "samsung,s3c2440-i2c";
550 clocks = <&clock CLK_I2C4>;
551 clock-names = "i2c";
552 pinctrl-names = "default";
553 pinctrl-0 = <&i2c4_bus>;
558 #address-cells = <1>;
559 #size-cells = <0>;
560 compatible = "samsung,s3c2440-i2c";
563 clocks = <&clock CLK_I2C5>;
564 clock-names = "i2c";
565 pinctrl-names = "default";
566 pinctrl-0 = <&i2c5_bus>;
571 #address-cells = <1>;
572 #size-cells = <0>;
573 compatible = "samsung,s3c2440-i2c";
576 clocks = <&clock CLK_I2C6>;
577 clock-names = "i2c";
578 pinctrl-names = "default";
579 pinctrl-0 = <&i2c6_bus>;
584 #address-cells = <1>;
585 #size-cells = <0>;
586 compatible = "samsung,s3c2440-i2c";
589 clocks = <&clock CLK_I2C7>;
590 clock-names = "i2c";
591 pinctrl-names = "default";
592 pinctrl-0 = <&i2c7_bus>;
597 #address-cells = <1>;
598 #size-cells = <0>;
599 compatible = "samsung,s3c2440-hdmiphy-i2c";
602 clocks = <&clock CLK_I2C_HDMI>;
603 clock-names = "i2c";
606 hdmi_i2c_phy: hdmi-phy@38 {
607 compatible = "samsung,exynos4210-hdmiphy";
613 compatible = "samsung,exynos4210-spi";
617 dma-names = "tx", "rx";
618 #address-cells = <1>;
619 #size-cells = <0>;
620 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
621 clock-names = "spi", "spi_busclk0";
622 pinctrl-names = "default";
623 pinctrl-0 = <&spi0_bus>;
624 fifo-depth = <256>;
629 compatible = "samsung,exynos4210-spi";
633 dma-names = "tx", "rx";
634 #address-cells = <1>;
635 #size-cells = <0>;
636 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
637 clock-names = "spi", "spi_busclk0";
638 pinctrl-names = "default";
639 pinctrl-0 = <&spi1_bus>;
640 fifo-depth = <64>;
645 compatible = "samsung,exynos4210-spi";
649 dma-names = "tx", "rx";
650 #address-cells = <1>;
651 #size-cells = <0>;
652 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
653 clock-names = "spi", "spi_busclk0";
654 pinctrl-names = "default";
655 pinctrl-0 = <&spi2_bus>;
656 fifo-depth = <64>;
661 compatible = "samsung,exynos4210-pwm";
668 clocks = <&clock CLK_PWM>;
669 clock-names = "timers";
670 #pwm-cells = <3>;
674 pdma0: dma-controller@12680000 {
678 clocks = <&clock CLK_PDMA0>;
679 clock-names = "apb_pclk";
680 #dma-cells = <1>;
683 pdma1: dma-controller@12690000 {
687 clocks = <&clock CLK_PDMA1>;
688 clock-names = "apb_pclk";
689 #dma-cells = <1>;
692 mdma1: dma-controller@12850000 {
696 clocks = <&clock CLK_MDMA>;
697 clock-names = "apb_pclk";
698 #dma-cells = <1>;
702 compatible = "samsung,exynos4210-fimd";
703 interrupt-parent = <&combiner>;
705 interrupt-names = "fifo", "vsync", "lcd_sys";
707 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
708 clock-names = "sclk_fimd", "fimd";
709 power-domains = <&pd_lcd0>;
716 interrupt-parent = <&combiner>;
720 #thermal-sensor-cells = <0>;
723 jpeg_codec: jpeg-codec@11840000 {
724 compatible = "samsung,exynos4210-jpeg";
727 clocks = <&clock CLK_JPEG>;
728 clock-names = "jpeg";
729 power-domains = <&pd_cam>;
734 compatible = "samsung,exynos4210-rotator";
737 clocks = <&clock CLK_ROTATOR>;
738 clock-names = "rotator";
743 compatible = "samsung,exynos4210-hdmi";
746 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
748 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
749 <&clock CLK_SCLK_PIXEL>,
750 <&clock CLK_SCLK_HDMIPHY>,
751 <&clock CLK_MOUT_HDMI>;
753 power-domains = <&pd_tv>;
754 samsung,syscon-phandle = <&pmu_system_controller>;
755 #sound-dai-cells = <0>;
760 compatible = "samsung,s5p-cec";
763 clocks = <&clock CLK_HDMI_CEC>;
764 clock-names = "hdmicec";
765 samsung,syscon-phandle = <&pmu_system_controller>;
766 hdmi-phandle = <&hdmi>;
767 pinctrl-names = "default";
768 pinctrl-0 = <&hdmi_cec>;
773 compatible = "samsung,exynos4210-mixer";
776 power-domains = <&pd_tv>;
782 compatible = "samsung,exynos-ppmu";
784 clocks = <&clock CLK_PPMUDMC0>;
785 clock-names = "ppmu";
790 compatible = "samsung,exynos-ppmu";
792 clocks = <&clock CLK_PPMUDMC1>;
793 clock-names = "ppmu";
798 compatible = "samsung,exynos-ppmu";
800 clocks = <&clock CLK_PPMUCPU>;
801 clock-names = "ppmu";
806 compatible = "samsung,exynos-ppmu";
808 clocks = <&clock CLK_PPMURIGHT>;
809 clock-names = "ppmu";
814 compatible = "samsung,exynos-ppmu";
816 clocks = <&clock CLK_PPMULEFT>;
817 clock-names = "ppmu";
822 compatible = "samsung,exynos-ppmu";
824 clocks = <&clock CLK_PPMUCAMIF>;
825 clock-names = "ppmu";
830 compatible = "samsung,exynos-ppmu";
832 clocks = <&clock CLK_PPMULCD0>;
833 clock-names = "ppmu";
838 compatible = "samsung,exynos-ppmu";
844 compatible = "samsung,exynos-ppmu";
846 clocks = <&clock CLK_PPMUIMAGE>;
847 clock-names = "ppmu";
852 compatible = "samsung,exynos-ppmu";
854 clocks = <&clock CLK_PPMUTV>;
855 clock-names = "ppmu";
860 compatible = "samsung,exynos-ppmu";
862 clocks = <&clock CLK_PPMUG3D>;
863 clock-names = "ppmu";
868 compatible = "samsung,exynos-ppmu";
870 clocks = <&clock CLK_PPMUMFC_L>;
871 clock-names = "ppmu";
876 compatible = "samsung,exynos-ppmu";
878 clocks = <&clock CLK_PPMUMFC_R>;
879 clock-names = "ppmu";
884 compatible = "samsung,exynos-sysmmu";
886 interrupt-parent = <&combiner>;
888 clock-names = "sysmmu", "master";
889 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
890 power-domains = <&pd_mfc>;
891 #iommu-cells = <0>;
895 compatible = "samsung,exynos-sysmmu";
897 interrupt-parent = <&combiner>;
899 clock-names = "sysmmu", "master";
900 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
901 power-domains = <&pd_mfc>;
902 #iommu-cells = <0>;
906 compatible = "samsung,exynos-sysmmu";
908 interrupt-parent = <&combiner>;
910 clock-names = "sysmmu", "master";
911 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
912 power-domains = <&pd_tv>;
913 #iommu-cells = <0>;
917 compatible = "samsung,exynos-sysmmu";
919 interrupt-parent = <&combiner>;
921 clock-names = "sysmmu", "master";
922 clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
923 power-domains = <&pd_cam>;
924 #iommu-cells = <0>;
928 compatible = "samsung,exynos-sysmmu";
930 interrupt-parent = <&combiner>;
932 clock-names = "sysmmu", "master";
933 clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
934 power-domains = <&pd_cam>;
935 #iommu-cells = <0>;
939 compatible = "samsung,exynos-sysmmu";
941 interrupt-parent = <&combiner>;
943 clock-names = "sysmmu", "master";
944 clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
945 power-domains = <&pd_cam>;
946 #iommu-cells = <0>;
950 compatible = "samsung,exynos-sysmmu";
952 interrupt-parent = <&combiner>;
954 clock-names = "sysmmu", "master";
955 clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
956 power-domains = <&pd_cam>;
957 #iommu-cells = <0>;
961 compatible = "samsung,exynos-sysmmu";
963 interrupt-parent = <&combiner>;
965 clock-names = "sysmmu", "master";
966 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
967 power-domains = <&pd_cam>;
968 #iommu-cells = <0>;
972 compatible = "samsung,exynos-sysmmu";
974 interrupt-parent = <&combiner>;
976 clock-names = "sysmmu", "master";
977 clocks = <&clock CLK_SMMU_ROTATOR>,
978 <&clock CLK_ROTATOR>;
979 #iommu-cells = <0>;
983 compatible = "samsung,exynos-sysmmu";
985 interrupt-parent = <&combiner>;
987 clock-names = "sysmmu", "master";
988 clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
989 power-domains = <&pd_lcd0>;
990 #iommu-cells = <0>;
994 compatible = "samsung,exynos4210-secss";
997 clocks = <&clock CLK_SSS>;
998 clock-names = "secss";
1002 compatible = "samsung,exynos4-rng";
1004 clocks = <&clock CLK_SSS>;
1005 clock-names = "secss";
1010 #include "exynos-syscon-restart.dtsi"