Lines Matching full:cru

6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
43 			clocks = <&cru ARMCLK>;
51 			clocks = <&cru ARMCLK>;
59 			clocks = <&cru ARMCLK>;
67 			clocks = <&cru ARMCLK>;
186 				clocks = <&cru HCLK_EMMC>,
187 					 <&cru CLK_EMMC>,
188 					 <&cru HCLK_NANDC>,
189 					 <&cru CLK_NANDC>,
190 					 <&cru HCLK_SFC>,
191 					 <&cru HCLK_SFCXIP>,
192 					 <&cru SCLK_SFC>;
201 				clocks = <&cru HCLK_SDIO>,
202 					 <&cru CLK_SDIO>;
209 				clocks = <&cru ACLK_RGA>,
210 					 <&cru HCLK_RGA>,
211 					 <&cru CLK_RGA_CORE>,
212 					 <&cru ACLK_VOP>,
213 					 <&cru HCLK_VOP>,
214 					 <&cru DCLK_VOP>,
215 					 <&cru PCLK_DSIHOST>,
216 					 <&cru ACLK_IEP>,
217 					 <&cru HCLK_IEP>,
218 					 <&cru CLK_IEP_CORE>;
368 	cru: clock-controller@ff490000 {  label
369 		compatible = "rockchip,rv1126-cru";
385 		clocks = <&cru ACLK_DMAC>;
393 		clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
407 		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
418 		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
429 		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
440 		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
452 		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
468 		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
484 		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
500 		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
516 		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
532 		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
534 		resets = <&cru SRST_SARADC_P>;
543 		clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
551 		clocks = <&cru MCLK_I2S0_TX>, <&cru MCLK_I2S0_RX>, <&cru HCLK_I2S0>;
566 		resets = <&cru SRST_I2S0_TX_M>, <&cru SRST_I2S0_RX_M>;
578 		clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
580 		resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
604 		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
617 		clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
618 			 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
619 			 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
620 			 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>;
625 		resets = <&cru SRST_GMAC_A>;
663 		clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
664 			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
676 		clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
677 			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
688 		clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
689 			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
701 		assigned-clocks = <&cru SCLK_SFC>;
704 		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
732 			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
743 			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
754 			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
765 			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;