Lines Matching full:cru
46 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
48 assigned-clocks = <&cru ACLK_GPU>;
50 resets = <&cru SRST_GPU>;
60 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
61 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
82 clocks = <&cru CORE_PERI>;
96 clocks = <&cru CORE_PERI>;
114 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
125 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
173 clocks = <&cru HCLK_OTG0>;
188 clocks = <&cru HCLK_OTG1>;
200 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
212 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
217 resets = <&cru SRST_SDMMC>;
226 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
231 resets = <&cru SRST_SDIO>;
240 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
245 resets = <&cru SRST_EMMC>;
254 clocks = <&cru HCLK_NANDC0>;
286 clocks = <&cru ACLK_DMA1>;
298 clocks = <&cru ACLK_DMA1>;
313 clocks = <&cru PCLK_I2C0>;
327 clocks = <&cru PCLK_I2C1>;
337 clocks = <&cru PCLK_PWM01>;
345 clocks = <&cru PCLK_PWM01>;
352 clocks = <&cru PCLK_WDT>;
361 clocks = <&cru PCLK_PWM23>;
369 clocks = <&cru PCLK_PWM23>;
382 clocks = <&cru PCLK_I2C2>;
397 clocks = <&cru PCLK_I2C3>;
412 clocks = <&cru PCLK_I2C4>;
425 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
436 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
445 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
447 resets = <&cru SRST_SARADC>;
454 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
467 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
486 clocks = <&cru ACLK_DMA2>;