Lines Matching full:cru
7 #include <dt-bindings/clock/rk3288-cru.h>
70 resets = <&cru SRST_CORE0>;
74 clocks = <&cru ARMCLK>;
81 resets = <&cru SRST_CORE1>;
85 clocks = <&cru ARMCLK>;
92 resets = <&cru SRST_CORE2>;
96 clocks = <&cru ARMCLK>;
103 resets = <&cru SRST_CORE3>;
107 clocks = <&cru ARMCLK>;
208 clocks = <&cru PCLK_TIMER>, <&xin24m>;
220 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
221 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
226 resets = <&cru SRST_MMC0>;
234 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
235 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
240 resets = <&cru SRST_SDIO0>;
248 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
249 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
254 resets = <&cru SRST_SDIO1>;
262 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
263 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
268 resets = <&cru SRST_EMMC>;
278 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
280 resets = <&cru SRST_SARADC>;
287 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
302 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
317 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
337 clocks = <&cru PCLK_I2C1>;
350 clocks = <&cru PCLK_I2C3>;
363 clocks = <&cru PCLK_I2C4>;
376 clocks = <&cru PCLK_I2C5>;
388 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
403 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
418 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
431 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
446 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
463 clocks = <&cru ACLK_DMAC2>;
552 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
554 resets = <&cru SRST_TSADC>;
573 clocks = <&cru SCLK_MAC>,
574 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
575 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
576 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
581 resets = <&cru SRST_MAC>;
590 clocks = <&cru HCLK_USBHOST0>;
601 clocks = <&cru HCLK_USBHOST0>;
612 clocks = <&cru HCLK_USBHOST1>;
626 clocks = <&cru HCLK_OTG0>;
641 clocks = <&cru HCLK_HSIC>;
653 clocks = <&cru ACLK_DMAC1>;
665 clocks = <&cru PCLK_I2C0>;
678 clocks = <&cru PCLK_I2C2>;
690 clocks = <&cru PCLK_RKPWM>;
700 clocks = <&cru PCLK_RKPWM>;
710 clocks = <&cru PCLK_RKPWM>;
720 clocks = <&cru PCLK_RKPWM>;
751 assigned-clocks = <&cru SCLK_EDP_24M>;
779 clocks = <&cru ACLK_IEP>,
780 <&cru ACLK_ISP>,
781 <&cru ACLK_RGA>,
782 <&cru ACLK_VIP>,
783 <&cru ACLK_VOP0>,
784 <&cru ACLK_VOP1>,
785 <&cru DCLK_VOP0>,
786 <&cru DCLK_VOP1>,
787 <&cru HCLK_IEP>,
788 <&cru HCLK_ISP>,
789 <&cru HCLK_RGA>,
790 <&cru HCLK_VIP>,
791 <&cru HCLK_VOP0>,
792 <&cru HCLK_VOP1>,
793 <&cru PCLK_EDP_CTRL>,
794 <&cru PCLK_HDMI_CTRL>,
795 <&cru PCLK_LVDS_PHY>,
796 <&cru PCLK_MIPI_CSI>,
797 <&cru PCLK_MIPI_DSI0>,
798 <&cru PCLK_MIPI_DSI1>,
799 <&cru SCLK_EDP_24M>,
800 <&cru SCLK_EDP>,
801 <&cru SCLK_ISP_JPE>,
802 <&cru SCLK_ISP>,
803 <&cru SCLK_RGA>;
822 clocks = <&cru ACLK_HEVC>,
823 <&cru SCLK_HEVC_CABAC>,
824 <&cru SCLK_HEVC_CORE>;
837 clocks = <&cru ACLK_VCODEC>,
838 <&cru HCLK_VCODEC>;
849 clocks = <&cru ACLK_GPU>;
871 cru: clock-controller@ff760000 { label
872 compatible = "rockchip,rk3288-cru";
879 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
880 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
881 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
882 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
883 <&cru PCLK_PERI>;
897 clocks = <&cru SCLK_EDP_24M>;
917 clocks = <&cru SCLK_OTGPHY0>;
920 resets = <&cru SRST_USBOTG_PHY>;
927 clocks = <&cru SCLK_OTGPHY1>;
930 resets = <&cru SRST_USBHOST0_PHY>;
937 clocks = <&cru SCLK_OTGPHY2>;
940 resets = <&cru SRST_USBHOST1_PHY>;
949 clocks = <&cru PCLK_WDT>;
958 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
974 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
989 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
990 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
992 resets = <&cru SRST_CRYPTO>;
1000 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1010 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1021 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1024 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1032 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1035 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1070 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1081 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1084 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1119 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1130 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1165 clocks = <&cru PCLK_LVDS_PHY>;
1203 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1208 resets = <&cru SRST_EDP>;
1244 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1283 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1293 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1303 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1316 clocks = <&cru ACLK_GPU>;
1426 clocks = <&cru ACLK_DMAC1>;
1435 clocks = <&cru PCLK_EFUSE256>;
1471 clocks = <&cru PCLK_GPIO0>;
1484 clocks = <&cru PCLK_GPIO1>;
1497 clocks = <&cru PCLK_GPIO2>;
1510 clocks = <&cru PCLK_GPIO3>;
1523 clocks = <&cru PCLK_GPIO4>;
1536 clocks = <&cru PCLK_GPIO5>;
1549 clocks = <&cru PCLK_GPIO6>;
1562 clocks = <&cru PCLK_GPIO7>;
1575 clocks = <&cru PCLK_GPIO8>;