Lines Matching full:cru
6 #include <dt-bindings/clock/rk3128-cru.h>
52 clocks = <&cru ARMCLK>;
53 resets = <&cru SRST_CORE0>;
62 resets = <&cru SRST_CORE1>;
70 resets = <&cru SRST_CORE2>;
78 resets = <&cru SRST_CORE3>;
190 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
193 resets = <&cru SRST_GPU>;
210 clocks = <&cru ACLK_CIF>,
211 <&cru HCLK_CIF>,
212 <&cru DCLK_EBC>,
213 <&cru HCLK_EBC>,
214 <&cru ACLK_IEP>,
215 <&cru HCLK_IEP>,
216 <&cru ACLK_LCDC0>,
217 <&cru HCLK_LCDC0>,
218 <&cru PCLK_MIPI>,
219 <&cru PCLK_MIPIPHY>,
220 <&cru SCLK_MIPI_24M>,
221 <&cru ACLK_RGA>,
222 <&cru HCLK_RGA>,
223 <&cru ACLK_VIO0>,
224 <&cru ACLK_VIO1>,
225 <&cru HCLK_VIO>,
226 <&cru HCLK_VIO_H2P>,
227 <&cru DCLK_VOP>,
228 <&cru SCLK_VOP>;
239 clocks = <&cru ACLK_VDPU>,
240 <&cru HCLK_VDPU>,
241 <&cru ACLK_VEPU>,
242 <&cru HCLK_VEPU>,
243 <&cru SCLK_HEVC_CORE>;
250 clocks = <&cru ACLK_GPU>;
263 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
264 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
275 clocks = <&cru ACLK_VEPU>, <&cru HCLK_VDPU>;
285 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>,
286 <&cru HCLK_LCDC0>;
289 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>,
290 <&cru SRST_VOP_D>;
316 clocks = <&cru PCLK_MIPI>;
321 resets = <&cru SRST_VIO_MIPI_DSI>;
395 clocks = <&cru HCLK_OTG>;
410 clocks = <&cru HCLK_HOST2>;
420 clocks = <&cru HCLK_HOST2>;
430 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S_8CH>;
442 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
456 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
465 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
466 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
472 resets = <&cru SRST_SDMMC>;
481 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
482 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
488 resets = <&cru SRST_SDIO>;
497 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
498 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
504 resets = <&cru SRST_EMMC>;
513 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S_2CH>;
528 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
536 cru: clock-controller@20000000 { label
537 compatible = "rockchip,rk3128-cru";
544 assigned-clocks = <&cru PLL_GPLL>;
557 clocks = <&cru SCLK_OTGPHY0>;
560 assigned-clocks = <&cru SCLK_USB480M>;
588 clocks = <&cru PCLK_HDMI>, <&cru DCLK_VOP>;
616 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>;
620 resets = <&cru SRST_MIPIPHY_P>;
629 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
637 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>;
645 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>;
653 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>;
661 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>;
669 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>;
677 clocks = <&cru PCLK_WDT>;
684 clocks = <&cru PCLK_PWM>;
694 clocks = <&cru PCLK_PWM>;
704 clocks = <&cru PCLK_PWM>;
714 clocks = <&cru PCLK_PWM>;
726 clocks = <&cru PCLK_I2C1>;
739 clocks = <&cru PCLK_I2C2>;
752 clocks = <&cru PCLK_I2C3>;
765 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
781 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
797 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
812 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
814 resets = <&cru SRST_SARADC>;
825 clocks = <&cru PCLK_I2C0>;
837 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
855 clocks = <&cru ACLK_DMAC>;
866 clocks = <&cru SCLK_MAC>,
867 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
868 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
869 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
874 resets = <&cru SRST_GMAC>;
899 clocks = <&cru PCLK_GPIO0>;
910 clocks = <&cru PCLK_GPIO1>;
921 clocks = <&cru PCLK_GPIO2>;
932 clocks = <&cru PCLK_GPIO3>;