Lines Matching +full:cru +full:- +full:bus
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "rockchip,rk3066-smp";
28 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
31 operating-points =
40 clock-latency = <40000>;
41 clocks = <&cru ARMCLK>;
45 compatible = "arm,cortex-a9";
46 next-level-cache = <&L2>;
51 display-subsystem {
52 compatible = "rockchip,display-subsystem";
56 hdmi_sound: hdmi-sound {
57 compatible = "simple-audio-card";
58 simple-audio-card,name = "HDMI";
59 simple-audio-card,format = "i2s";
60 simple-audio-card,mclk-fs = <256>;
63 simple-audio-card,codec {
64 sound-dai = <&hdmi>;
67 simple-audio-card,cpu {
68 sound-dai = <&i2s0>;
73 compatible = "mmio-sram";
75 #address-cells = <1>;
76 #size-cells = <1>;
79 smp-sram@0 {
80 compatible = "rockchip,rk3066-smp-sram";
86 compatible = "rockchip,rk3066-vop";
89 clocks = <&cru ACLK_LCDC0>,
90 <&cru DCLK_LCDC0>,
91 <&cru HCLK_LCDC0>;
92 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
93 power-domains = <&power RK3066_PD_VIO>;
94 resets = <&cru SRST_LCDC0_AXI>,
95 <&cru SRST_LCDC0_AHB>,
96 <&cru SRST_LCDC0_DCLK>;
97 reset-names = "axi", "ahb", "dclk";
101 #address-cells = <1>;
102 #size-cells = <0>;
106 remote-endpoint = <&hdmi_in_vop0>;
112 compatible = "rockchip,rk3066-vop";
115 clocks = <&cru ACLK_LCDC1>,
116 <&cru DCLK_LCDC1>,
117 <&cru HCLK_LCDC1>;
118 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
119 power-domains = <&power RK3066_PD_VIO>;
120 resets = <&cru SRST_LCDC1_AXI>,
121 <&cru SRST_LCDC1_AHB>,
122 <&cru SRST_LCDC1_DCLK>;
123 reset-names = "axi", "ahb", "dclk";
127 #address-cells = <1>;
128 #size-cells = <0>;
132 remote-endpoint = <&hdmi_in_vop1>;
138 compatible = "rockchip,rk3066-hdmi";
141 clocks = <&cru HCLK_HDMI>;
142 clock-names = "hclk";
143 pinctrl-names = "default";
144 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
145 power-domains = <&power RK3066_PD_VIO>;
147 #sound-dai-cells = <0>;
151 #address-cells = <1>;
152 #size-cells = <0>;
156 #address-cells = <1>;
157 #size-cells = <0>;
161 remote-endpoint = <&vop0_out_hdmi>;
166 remote-endpoint = <&vop1_out_hdmi>;
177 compatible = "rockchip,rk3066-i2s";
180 pinctrl-names = "default";
181 pinctrl-0 = <&i2s0_bus>;
182 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
183 clock-names = "i2s_clk", "i2s_hclk";
185 dma-names = "tx", "rx";
186 rockchip,playback-channels = <8>;
187 rockchip,capture-channels = <2>;
188 #sound-dai-cells = <0>;
193 compatible = "rockchip,rk3066-i2s";
196 pinctrl-names = "default";
197 pinctrl-0 = <&i2s1_bus>;
198 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
199 clock-names = "i2s_clk", "i2s_hclk";
201 dma-names = "tx", "rx";
202 rockchip,playback-channels = <2>;
203 rockchip,capture-channels = <2>;
204 #sound-dai-cells = <0>;
209 compatible = "rockchip,rk3066-i2s";
212 pinctrl-names = "default";
213 pinctrl-0 = <&i2s2_bus>;
214 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
215 clock-names = "i2s_clk", "i2s_hclk";
217 dma-names = "tx", "rx";
218 rockchip,playback-channels = <2>;
219 rockchip,capture-channels = <2>;
220 #sound-dai-cells = <0>;
224 cru: clock-controller@20000000 { label
225 compatible = "rockchip,rk3066a-cru";
228 clock-names = "xin24m";
230 #clock-cells = <1>;
231 #reset-cells = <1>;
232 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
233 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
234 <&cru PCLK_CPU>, <&cru ACLK_PERI>,
235 <&cru HCLK_PERI>, <&cru PCLK_PERI>;
236 assigned-clock-rates = <400000000>, <594000000>,
243 compatible = "snps,dw-apb-timer";
246 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
247 clock-names = "timer", "pclk";
251 compatible = "rockchip,rk3066a-efuse";
253 #address-cells = <1>;
254 #size-cells = <1>;
255 clocks = <&cru PCLK_EFUSE>;
256 clock-names = "pclk_efuse";
264 compatible = "snps,dw-apb-timer";
267 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
268 clock-names = "timer", "pclk";
272 compatible = "snps,dw-apb-timer";
275 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
276 clock-names = "timer", "pclk";
280 compatible = "rockchip,rk3066-tsadc";
282 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
283 clock-names = "saradc", "apb_pclk";
285 #io-channel-cells = <1>;
286 resets = <&cru SRST_TSADC>;
287 reset-names = "saradc-apb";
292 compatible = "rockchip,rk3066a-pinctrl";
294 #address-cells = <1>;
295 #size-cells = <1>;
299 compatible = "rockchip,gpio-bank";
302 clocks = <&cru PCLK_GPIO0>;
304 gpio-controller;
305 #gpio-cells = <2>;
307 interrupt-controller;
308 #interrupt-cells = <2>;
312 compatible = "rockchip,gpio-bank";
315 clocks = <&cru PCLK_GPIO1>;
317 gpio-controller;
318 #gpio-cells = <2>;
320 interrupt-controller;
321 #interrupt-cells = <2>;
325 compatible = "rockchip,gpio-bank";
328 clocks = <&cru PCLK_GPIO2>;
330 gpio-controller;
331 #gpio-cells = <2>;
333 interrupt-controller;
334 #interrupt-cells = <2>;
338 compatible = "rockchip,gpio-bank";
341 clocks = <&cru PCLK_GPIO3>;
343 gpio-controller;
344 #gpio-cells = <2>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
351 compatible = "rockchip,gpio-bank";
354 clocks = <&cru PCLK_GPIO4>;
356 gpio-controller;
357 #gpio-cells = <2>;
359 interrupt-controller;
360 #interrupt-cells = <2>;
364 compatible = "rockchip,gpio-bank";
367 clocks = <&cru PCLK_GPIO6>;
369 gpio-controller;
370 #gpio-cells = <2>;
372 interrupt-controller;
373 #interrupt-cells = <2>;
376 pcfg_pull_default: pcfg-pull-default {
377 bias-pull-pin-default;
380 pcfg_pull_none: pcfg-pull-none {
381 bias-disable;
385 emac_xfer: emac-xfer {
396 emac_mdio: emac-mdio {
403 emmc_clk: emmc-clk {
407 emmc_cmd: emmc-cmd {
411 emmc_rst: emmc-rst {
419 * flash/emmc is the boot-device.
424 hdmi_hpd: hdmi-hpd {
428 hdmii2c_xfer: hdmii2c-xfer {
435 i2c0_xfer: i2c0-xfer {
442 i2c1_xfer: i2c1-xfer {
449 i2c2_xfer: i2c2-xfer {
456 i2c3_xfer: i2c3-xfer {
463 i2c4_xfer: i2c4-xfer {
470 pwm0_out: pwm0-out {
476 pwm1_out: pwm1-out {
482 pwm2_out: pwm2-out {
488 pwm3_out: pwm3-out {
494 spi0_clk: spi0-clk {
497 spi0_cs0: spi0-cs0 {
500 spi0_tx: spi0-tx {
503 spi0_rx: spi0-rx {
506 spi0_cs1: spi0-cs1 {
512 spi1_clk: spi1-clk {
515 spi1_cs0: spi1-cs0 {
518 spi1_rx: spi1-rx {
521 spi1_tx: spi1-tx {
524 spi1_cs1: spi1-cs1 {
530 uart0_xfer: uart0-xfer {
535 uart0_cts: uart0-cts {
539 uart0_rts: uart0-rts {
545 uart1_xfer: uart1-xfer {
550 uart1_cts: uart1-cts {
554 uart1_rts: uart1-rts {
560 uart2_xfer: uart2-xfer {
568 uart3_xfer: uart3-xfer {
573 uart3_cts: uart3-cts {
577 uart3_rts: uart3-rts {
583 sd0_clk: sd0-clk {
587 sd0_cmd: sd0-cmd {
591 sd0_cd: sd0-cd {
595 sd0_wp: sd0-wp {
599 sd0_bus1: sd0-bus-width1 {
603 sd0_bus4: sd0-bus-width4 {
612 sd1_clk: sd1-clk {
616 sd1_cmd: sd1-cmd {
620 sd1_cd: sd1-cd {
624 sd1_wp: sd1-wp {
628 sd1_bus1: sd1-bus-width1 {
632 sd1_bus4: sd1-bus-width4 {
641 i2s0_bus: i2s0-bus {
655 i2s1_bus: i2s1-bus {
666 i2s2_bus: i2s2-bus {
679 compatible = "rockchip,rk3066-mali", "arm,mali-400";
690 interrupt-names = "gp",
700 power-domains = <&power RK3066_PD_GPU>;
704 compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd";
707 compatible = "rockchip,rk3066a-usb-phy";
708 #address-cells = <1>;
709 #size-cells = <0>;
712 usbphy0: usb-phy@17c {
714 clocks = <&cru SCLK_OTGPHY0>;
715 clock-names = "phyclk";
716 #clock-cells = <0>;
717 #phy-cells = <0>;
720 usbphy1: usb-phy@188 {
722 clocks = <&cru SCLK_OTGPHY1>;
723 clock-names = "phyclk";
724 #clock-cells = <0>;
725 #phy-cells = <0>;
731 pinctrl-names = "default";
732 pinctrl-0 = <&i2c0_xfer>;
736 pinctrl-names = "default";
737 pinctrl-0 = <&i2c1_xfer>;
741 pinctrl-names = "default";
742 pinctrl-0 = <&i2c2_xfer>;
746 pinctrl-names = "default";
747 pinctrl-0 = <&i2c3_xfer>;
751 pinctrl-names = "default";
752 pinctrl-0 = <&i2c4_xfer>;
756 clock-frequency = <50000000>;
758 dma-names = "rx-tx";
759 max-frequency = <50000000>;
760 pinctrl-names = "default";
761 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
766 dma-names = "rx-tx";
767 pinctrl-names = "default";
768 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
773 dma-names = "rx-tx";
777 power: power-controller {
778 compatible = "rockchip,rk3066-power-controller";
779 #power-domain-cells = <1>;
780 #address-cells = <1>;
781 #size-cells = <0>;
783 power-domain@RK3066_PD_VIO {
785 clocks = <&cru ACLK_LCDC0>,
786 <&cru ACLK_LCDC1>,
787 <&cru DCLK_LCDC0>,
788 <&cru DCLK_LCDC1>,
789 <&cru HCLK_LCDC0>,
790 <&cru HCLK_LCDC1>,
791 <&cru SCLK_CIF1>,
792 <&cru ACLK_CIF1>,
793 <&cru HCLK_CIF1>,
794 <&cru SCLK_CIF0>,
795 <&cru ACLK_CIF0>,
796 <&cru HCLK_CIF0>,
797 <&cru HCLK_HDMI>,
798 <&cru ACLK_IPP>,
799 <&cru HCLK_IPP>,
800 <&cru ACLK_RGA>,
801 <&cru HCLK_RGA>;
808 #power-domain-cells = <0>;
811 power-domain@RK3066_PD_VIDEO {
813 clocks = <&cru ACLK_VDPU>,
814 <&cru ACLK_VEPU>,
815 <&cru HCLK_VDPU>,
816 <&cru HCLK_VEPU>;
818 #power-domain-cells = <0>;
821 power-domain@RK3066_PD_GPU {
823 clocks = <&cru ACLK_GPU>;
825 #power-domain-cells = <0>;
831 pinctrl-names = "default";
832 pinctrl-0 = <&pwm0_out>;
836 pinctrl-names = "default";
837 pinctrl-0 = <&pwm1_out>;
841 pinctrl-names = "default";
842 pinctrl-0 = <&pwm2_out>;
846 pinctrl-names = "default";
847 pinctrl-0 = <&pwm3_out>;
851 pinctrl-names = "default";
852 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
856 pinctrl-names = "default";
857 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
861 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
863 dma-names = "tx", "rx";
864 pinctrl-names = "default";
865 pinctrl-0 = <&uart0_xfer>;
869 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
871 dma-names = "tx", "rx";
872 pinctrl-names = "default";
873 pinctrl-0 = <&uart1_xfer>;
877 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
879 dma-names = "tx", "rx";
880 pinctrl-names = "default";
881 pinctrl-0 = <&uart2_xfer>;
885 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
887 dma-names = "tx", "rx";
888 pinctrl-names = "default";
889 pinctrl-0 = <&uart3_xfer>;
893 power-domains = <&power RK3066_PD_VIDEO>;
897 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";