Lines Matching full:cru
9 #include <dt-bindings/clock/rk3066a-cru.h>
41 clocks = <&cru ARMCLK>;
89 clocks = <&cru ACLK_LCDC0>,
90 <&cru DCLK_LCDC0>,
91 <&cru HCLK_LCDC0>;
94 resets = <&cru SRST_LCDC0_AXI>,
95 <&cru SRST_LCDC0_AHB>,
96 <&cru SRST_LCDC0_DCLK>;
115 clocks = <&cru ACLK_LCDC1>,
116 <&cru DCLK_LCDC1>,
117 <&cru HCLK_LCDC1>;
120 resets = <&cru SRST_LCDC1_AXI>,
121 <&cru SRST_LCDC1_AHB>,
122 <&cru SRST_LCDC1_DCLK>;
141 clocks = <&cru HCLK_HDMI>;
182 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
198 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
214 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
224 cru: clock-controller@20000000 { label
225 compatible = "rockchip,rk3066a-cru";
232 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
233 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
234 <&cru PCLK_CPU>, <&cru ACLK_PERI>,
235 <&cru HCLK_PERI>, <&cru PCLK_PERI>;
246 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
255 clocks = <&cru PCLK_EFUSE>;
267 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
275 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
282 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
286 resets = <&cru SRST_TSADC>;
302 clocks = <&cru PCLK_GPIO0>;
315 clocks = <&cru PCLK_GPIO1>;
328 clocks = <&cru PCLK_GPIO2>;
341 clocks = <&cru PCLK_GPIO3>;
354 clocks = <&cru PCLK_GPIO4>;
367 clocks = <&cru PCLK_GPIO6>;
714 clocks = <&cru SCLK_OTGPHY0>;
722 clocks = <&cru SCLK_OTGPHY1>;
785 clocks = <&cru ACLK_LCDC0>,
786 <&cru ACLK_LCDC1>,
787 <&cru DCLK_LCDC0>,
788 <&cru DCLK_LCDC1>,
789 <&cru HCLK_LCDC0>,
790 <&cru HCLK_LCDC1>,
791 <&cru SCLK_CIF1>,
792 <&cru ACLK_CIF1>,
793 <&cru HCLK_CIF1>,
794 <&cru SCLK_CIF0>,
795 <&cru ACLK_CIF0>,
796 <&cru HCLK_CIF0>,
797 <&cru HCLK_HDMI>,
798 <&cru ACLK_IPP>,
799 <&cru HCLK_IPP>,
800 <&cru ACLK_RGA>,
801 <&cru HCLK_RGA>;
813 clocks = <&cru ACLK_VDPU>,
814 <&cru ACLK_VEPU>,
815 <&cru HCLK_VDPU>,
816 <&cru HCLK_VEPU>;
823 clocks = <&cru ACLK_GPU>;