dts/rockchip/rk3036.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h>
12 	#address-cells = <1>;
13 	#size-cells = <1>;
15 	compatible = "rockchip,rk3036";
17 	interrupt-parent = <&gic>;
36 		#address-cells = <1>;
37 		#size-cells = <0>;
38 		enable-method = "rockchip,rk3036-smp";
42 			compatible = "arm,cortex-a7";
44 			resets = <&cru SRST_CORE0>;
45 			operating-points = <
49 			clock-latency = <40000>;
50 			clocks = <&cru ARMCLK>;
55 			compatible = "arm,cortex-a7";
57 			resets = <&cru SRST_CORE1>;
61 	arm-pmu {
62 		compatible = "arm,cortex-a7-pmu";
65 		interrupt-affinity = <&cpu0>, <&cpu1>;
68 	display-subsystem {
69 		compatible = "rockchip,display-subsystem";
74 		compatible = "arm,armv7-timer";
75 		arm,cpu-registers-not-fw-configured;
80 		clock-frequency = <24000000>;
84 		compatible = "fixed-clock";
85 		clock-frequency = <24000000>;
86 		clock-output-names = "xin24m";
87 		#clock-cells = <0>;
91 		compatible = "mmio-sram";
93 		#address-cells = <1>;
94 		#size-cells = <1>;
97 		smp-sram@0 {
98 			compatible = "rockchip,rk3066-smp-sram";
104 		compatible = "rockchip,rk3036-mali", "arm,mali-400";
110 		interrupt-names = "gp",
114 		assigned-clocks = <&cru SCLK_GPU>;
115 		assigned-clock-rates = <100000000>;
116 		clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
117 		clock-names = "bus", "core";
118 		power-domains = <&power RK3036_PD_GPU>;
119 		resets = <&cru SRST_GPU>;
123 	vpu: video-codec@10108000 {
124 		compatible = "rockchip,rk3036-vpu";
127 		interrupt-names = "vdpu";
128 		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
129 		clock-names = "aclk", "hclk";
131 		power-domains = <&power RK3036_PD_VPU>;
138 		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
139 		clock-names = "aclk", "iface";
140 		power-domains = <&power RK3036_PD_VPU>;
141 		#iommu-cells = <0>;
145 		compatible = "rockchip,rk3036-vop";
148 		clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
149 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
150 		resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
151 		reset-names = "axi", "ahb", "dclk";
153 		power-domains = <&power RK3036_PD_VIO>;
157 			#address-cells = <1>;
158 			#size-cells = <0>;
161 				remote-endpoint = <&hdmi_in_vop>;
170 		clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
171 		clock-names = "aclk", "iface";
172 		power-domains = <&power RK3036_PD_VIO>;
173 		#iommu-cells = <0>;
178 		compatible = "rockchip,rk3036-qos", "syscon";
183 		compatible = "rockchip,rk3036-qos", "syscon";
188 		compatible = "rockchip,rk3036-qos", "syscon";
192 	gic: interrupt-controller@10139000 {
193 		compatible = "arm,gic-400";
194 		interrupt-controller;
195 		#interrupt-cells = <3>;
196 		#address-cells = <0>;
206 		compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
210 		clocks = <&cru HCLK_OTG0>;
211 		clock-names = "otg";
213 		g-np-tx-fifo-size = <16>;
214 		g-rx-fifo-size = <275>;
215 		g-tx-fifo-size = <256 128 128 64 64 32>;
220 		compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
224 		clocks = <&cru HCLK_OTG1>;
225 		clock-names = "otg";
231 		compatible = "rockchip,rk3036-emac";
235 		clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
236 		clock-names = "hclk", "macref", "macclk";
242 		assigned-clocks = <&cru SCLK_MACPLL>;
243 		assigned-clock-parents = <&cru PLL_DPLL>;
244 		max-speed = <100>;
245 		phy-mode = "rmii";
250 		compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
252 		clock-frequency = <37500000>;
253 		max-frequency = <37500000>;
254 		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
255 		clock-names = "biu", "ciu";
256 		fifo-depth = <0x100>;
258 		resets = <&cru SRST_MMC0>;
259 		reset-names = "reset";
264 		compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
266 		max-frequency = <37500000>;
267 		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
268 			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
269 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
270 		fifo-depth = <0x100>;
272 		resets = <&cru SRST_SDIO>;
273 		reset-names = "reset";
278 		compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
281 		bus-width = <8>;
282 		cap-mmc-highspeed;
283 		clock-frequency = <37500000>;
284 		max-frequency = <37500000>;
285 		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
286 			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
287 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
288 		disable-wp;
290 		dma-names = "rx-tx";
291 		fifo-depth = <0x100>;
292 		mmc-ddr-1_8v;
293 		non-removable;
294 		pinctrl-names = "default";
295 		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
296 		resets = <&cru SRST_EMMC>;
297 		reset-names = "reset";
302 		compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
305 		clock-names = "i2s_clk", "i2s_hclk";
306 		clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
308 		dma-names = "tx", "rx";
309 		pinctrl-names = "default";
310 		pinctrl-0 = <&i2s_bus>;
311 		#sound-dai-cells = <0>;
315 	nfc: nand-controller@10500000 {
316 		compatible = "rockchip,rk3036-nfc",
317 			     "rockchip,rk2928-nfc";
320 		clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
321 		clock-names = "ahb", "nfc";
322 		assigned-clocks = <&cru SCLK_NANDC>;
323 		assigned-clock-rates = <150000000>;
324 		pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
326 		pinctrl-names = "default";
330 	cru: clock-controller@20000000 {  label
331 		compatible = "rockchip,rk3036-cru";
334 		clock-names = "xin24m";
336 		#clock-cells = <1>;
337 		#reset-cells = <1>;
338 		assigned-clocks = <&cru PLL_GPLL>;
339 		assigned-clock-rates = <594000000>;
343 		compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
346 		power: power-controller {
347 			compatible = "rockchip,rk3036-power-controller";
348 			#power-domain-cells = <1>;
349 			#address-cells = <1>;
350 			#size-cells = <0>;
352 			power-domain@RK3036_PD_VIO {
354 				clocks = <&cru ACLK_LCDC>,
355 					 <&cru HCLK_LCDC>,
356 					 <&cru SCLK_LCDC>;
358 				#power-domain-cells = <0>;
361 			power-domain@RK3036_PD_VPU {
363 				clocks = <&cru ACLK_VCODEC>,
364 					 <&cru HCLK_VCODEC>;
366 				#power-domain-cells = <0>;
369 			power-domain@RK3036_PD_GPU {
371 				clocks = <&cru SCLK_GPU>;
373 				#power-domain-cells = <0>;
377 		reboot-mode {
378 			compatible = "syscon-reboot-mode";
380 			mode-normal = <BOOT_NORMAL>;
381 			mode-recovery = <BOOT_RECOVERY>;
382 			mode-bootloader = <BOOT_FASTBOOT>;
383 			mode-loader = <BOOT_BL_DOWNLOAD>;
387 	acodec: audio-codec@20030000 {
388 		compatible = "rockchip,rk3036-codec";
390 		clock-names = "acodec_pclk";
391 		clocks = <&cru PCLK_ACODEC>;
393 		#sound-dai-cells = <0>;
398 		compatible = "rockchip,rk3036-inno-hdmi";
401 		clocks = <&cru  PCLK_HDMI>;
402 		clock-names = "pclk";
403 		pinctrl-names = "default";
404 		pinctrl-0 = <&hdmi_ctl>;
405 		#sound-dai-cells = <0>;
409 			#address-cells = <1>;
410 			#size-cells = <0>;
416 					remote-endpoint = <&vop_out_hdmi>;
427 		compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
430 		clocks = <&cru PCLK_TIMER>, <&xin24m>;
431 		clock-names = "pclk", "timer";
435 		compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
437 		#pwm-cells = <3>;
438 		clocks = <&cru PCLK_PWM>;
439 		pinctrl-names = "default";
440 		pinctrl-0 = <&pwm0_pin>;
445 		compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
447 		#pwm-cells = <3>;
448 		clocks = <&cru PCLK_PWM>;
449 		pinctrl-names = "default";
450 		pinctrl-0 = <&pwm1_pin>;
455 		compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
457 		#pwm-cells = <3>;
458 		clocks = <&cru PCLK_PWM>;
459 		pinctrl-names = "default";
460 		pinctrl-0 = <&pwm2_pin>;
465 		compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
467 		#pwm-cells = <2>;
468 		clocks = <&cru PCLK_PWM>;
469 		pinctrl-names = "default";
470 		pinctrl-0 = <&pwm3_pin>;
475 		compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
478 		#address-cells = <1>;
479 		#size-cells = <0>;
480 		clock-names = "i2c";
481 		clocks = <&cru PCLK_I2C1>;
482 		pinctrl-names = "default";
483 		pinctrl-0 = <&i2c1_xfer>;
488 		compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
491 		#address-cells = <1>;
492 		#size-cells = <0>;
493 		clock-names = "i2c";
494 		clocks = <&cru PCLK_I2C2>;
495 		pinctrl-names = "default";
496 		pinctrl-0 = <&i2c2_xfer>;
501 		compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
504 		reg-shift = <2>;
505 		reg-io-width = <4>;
506 		clock-frequency = <24000000>;
507 		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
508 		clock-names = "baudclk", "apb_pclk";
509 		pinctrl-names = "default";
510 		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
515 		compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
518 		reg-shift = <2>;
519 		reg-io-width = <4>;
520 		clock-frequency = <24000000>;
521 		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
522 		clock-names = "baudclk", "apb_pclk";
523 		pinctrl-names = "default";
524 		pinctrl-0 = <&uart1_xfer>;
529 		compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
532 		reg-shift = <2>;
533 		reg-io-width = <4>;
534 		clock-frequency = <24000000>;
535 		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
536 		clock-names = "baudclk", "apb_pclk";
537 		pinctrl-names = "default";
538 		pinctrl-0 = <&uart2_xfer>;
543 		compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
546 		#address-cells = <1>;
547 		#size-cells = <0>;
548 		clock-names = "i2c";
549 		clocks = <&cru PCLK_I2C0>;
550 		pinctrl-names = "default";
551 		pinctrl-0 = <&i2c0_xfer>;
556 		compatible = "rockchip,rk3036-spi";
559 		clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
560 		clock-names = "spiclk", "apb_pclk";
562 		dma-names = "tx", "rx";
563 		pinctrl-names = "default";
564 		pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
565 		#address-cells = <1>;
566 		#size-cells = <0>;
570 	pdma: dma-controller@20078000 {
575 		#dma-cells = <1>;
576 		arm,pl330-broken-no-flushp;
577 		arm,pl330-periph-burst;
578 		clocks = <&cru ACLK_DMAC2>;
579 		clock-names = "apb_pclk";
583 		compatible = "rockchip,rk3036-pinctrl";
585 		#address-cells = <1>;
586 		#size-cells = <1>;
590 			compatible = "rockchip,gpio-bank";
593 			clocks = <&cru PCLK_GPIO0>;
595 			gpio-controller;
596 			#gpio-cells = <2>;
598 			interrupt-controller;
599 			#interrupt-cells = <2>;
603 			compatible = "rockchip,gpio-bank";
606 			clocks = <&cru PCLK_GPIO1>;
608 			gpio-controller;
609 			#gpio-cells = <2>;
611 			interrupt-controller;
612 			#interrupt-cells = <2>;
616 			compatible = "rockchip,gpio-bank";
619 			clocks = <&cru PCLK_GPIO2>;
621 			gpio-controller;
622 			#gpio-cells = <2>;
624 			interrupt-controller;
625 			#interrupt-cells = <2>;
628 		pcfg_pull_default: pcfg-pull-default {
629 			bias-pull-pin-default;
632 		pcfg_pull_none: pcfg-pull-none {
633 			bias-disable;
637 			pwm0_pin: pwm0-pin {
643 			pwm1_pin: pwm1-pin {
649 			pwm2_pin: pwm2-pin {
655 			pwm3_pin: pwm3-pin {
661 			sdmmc_clk: sdmmc-clk {
665 			sdmmc_cmd: sdmmc-cmd {
669 			sdmmc_cd: sdmmc-cd {
673 			sdmmc_bus1: sdmmc-bus1 {
677 			sdmmc_bus4: sdmmc-bus4 {
686 			sdio_bus1: sdio-bus1 {
690 			sdio_bus4: sdio-bus4 {
697 			sdio_cmd: sdio-cmd {
701 			sdio_clk: sdio-clk {
711 			emmc_clk: emmc-clk {
715 			emmc_cmd: emmc-cmd {
719 			emmc_bus8: emmc-bus8 {
732 			flash_ale: flash-ale {
736 			flash_bus8: flash-bus8 {
747 			flash_cle: flash-cle {
751 			flash_csn0: flash-csn0 {
755 			flash_rdn: flash-rdn {
759 			flash_rdy: flash-rdy {
763 			flash_wrn: flash-wrn {
769 			emac_xfer: emac-xfer {
780 			emac_mdio: emac-mdio {
787 			i2c0_xfer: i2c0-xfer {
794 			i2c1_xfer: i2c1-xfer {
801 			i2c2_xfer: i2c2-xfer {
808 			i2s_bus: i2s-bus {
819 			hdmi_ctl: hdmi-ctl {
828 			uart0_xfer: uart0-xfer {
833 			uart0_cts: uart0-cts {
837 			uart0_rts: uart0-rts {
843 			uart1_xfer: uart1-xfer {
851 			uart2_xfer: uart2-xfer {
858 		spi-pins {
859 			spi_txd:spi-txd {
863 			spi_rxd:spi-rxd {
867 			spi_clk:spi-clk {
871 			spi_cs0:spi-cs0 {
876 			spi_cs1:spi-cs1 {