Lines Matching full:gcc
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
54 clocks = <&gcc GCC_APPS_CLK_SRC>;
68 clocks = <&gcc GCC_APPS_CLK_SRC>;
82 clocks = <&gcc GCC_APPS_CLK_SRC>;
96 clocks = <&gcc GCC_APPS_CLK_SRC>;
187 gcc: clock-controller@1800000 { label
188 compatible = "qcom,gcc-ipq4019";
199 clocks = <&gcc GCC_PRNG_AHB_CLK>;
232 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
233 <&gcc GCC_SDCC1_APPS_CLK>,
245 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
256 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
257 <&gcc GCC_BLSP1_AHB_CLK>;
270 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
271 <&gcc GCC_BLSP1_AHB_CLK>;
284 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
285 <&gcc GCC_BLSP1_AHB_CLK>;
298 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
299 <&gcc GCC_BLSP1_AHB_CLK>;
312 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
323 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
324 <&gcc GCC_CRYPTO_AXI_CLK>,
325 <&gcc GCC_CRYPTO_CLK>;
382 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
383 <&gcc GCC_BLSP1_AHB_CLK>;
394 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
395 <&gcc GCC_BLSP1_AHB_CLK>;
439 clocks = <&gcc GCC_PCIE_AHB_CLK>,
440 <&gcc GCC_PCIE_AXI_M_CLK>,
441 <&gcc GCC_PCIE_AXI_S_CLK>;
446 resets = <&gcc PCIE_AXI_M_ARES>,
447 <&gcc PCIE_AXI_S_ARES>,
448 <&gcc PCIE_PIPE_ARES>,
449 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
450 <&gcc PCIE_AXI_S_XPU_ARES>,
451 <&gcc PCIE_PARF_XPU_ARES>,
452 <&gcc PCIE_PHY_ARES>,
453 <&gcc PCIE_AXI_M_STICKY_ARES>,
454 <&gcc PCIE_PIPE_STICKY_ARES>,
455 <&gcc PCIE_PWR_ARES>,
456 <&gcc PCIE_AHB_ARES>,
457 <&gcc PCIE_PHY_AHB_ARES>;
488 clocks = <&gcc GCC_QPIC_CLK>;
500 clocks = <&gcc GCC_QPIC_CLK>,
501 <&gcc GCC_QPIC_AHB_CLK>;
522 resets = <&gcc WIFI0_CPU_INIT_RESET>,
523 <&gcc WIFI0_RADIO_SRIF_RESET>,
524 <&gcc WIFI0_RADIO_WARM_RESET>,
525 <&gcc WIFI0_RADIO_COLD_RESET>,
526 <&gcc WIFI0_CORE_WARM_RESET>,
527 <&gcc WIFI0_CORE_COLD_RESET>;
531 clocks = <&gcc GCC_WCSS2G_CLK>,
532 <&gcc GCC_WCSS2G_REF_CLK>,
533 <&gcc GCC_WCSS2G_RTC_CLK>;
564 resets = <&gcc WIFI1_CPU_INIT_RESET>,
565 <&gcc WIFI1_RADIO_SRIF_RESET>,
566 <&gcc WIFI1_RADIO_WARM_RESET>,
567 <&gcc WIFI1_RADIO_COLD_RESET>,
568 <&gcc WIFI1_CORE_WARM_RESET>,
569 <&gcc WIFI1_CORE_COLD_RESET>;
573 clocks = <&gcc GCC_WCSS5G_CLK>,
574 <&gcc GCC_WCSS5G_REF_CLK>,
575 <&gcc GCC_WCSS5G_RTC_CLK>;
645 resets = <&gcc USB3_UNIPHY_PHY_ARES>;
655 resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
665 clocks = <&gcc GCC_USB3_MASTER_CLK>,
666 <&gcc GCC_USB3_SLEEP_CLK>,
667 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
687 resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
697 clocks = <&gcc GCC_USB2_MASTER_CLK>,
698 <&gcc GCC_USB2_SLEEP_CLK>,
699 <&gcc GCC_USB2_MOCK_UTMI_CLK>;