Lines Matching +full:0 +full:x21a2
15 pinctrl-0 = <&pinctrl_mdio_mux>;
22 #size-cells = <0>;
27 #size-cells = <0>;
29 switch0: switch@0 {
31 pinctrl-0 = <&pinctrl_gpio_switch0>;
33 reg = <0>;
34 dsa,member = <0 0>;
43 #size-cells = <0>;
45 port@0 {
46 reg = <0>;
95 #size-cells = <0>;
127 #size-cells = <0>;
129 switch1: switch@0 {
131 pinctrl-0 = <&pinctrl_gpio_switch1>;
133 reg = <0>;
134 dsa,member = <0 1>;
143 #size-cells = <0>;
191 #size-cells = <0>;
223 #size-cells = <0>;
245 bus-num = <0>;
247 pinctrl-0 = <&pinctrl_dspi0>;
251 flash@0 {
255 reg = <0>;
263 pinctrl-0 = <&pinctr_atzb_rf_233>;
269 xtal-trim = /bits/ 8 <0x06>;
289 reg = <0x18>;
318 pinctrl-0 = <&pinctrl_sx1503_20>;
321 reg = <0x20>;
337 reg = <0x22>;
347 reg = <0x50>;
355 pinctrl-0 = <&pinctrl_i2c_mux_reset>;
358 #size-cells = <0>;
359 reg = <0x70>;
362 i2c@0 {
364 #size-cells = <0>;
365 reg = <0>;
370 #size-cells = <0>;
376 #size-cells = <0>;
382 #size-cells = <0>;
390 pinctrl-0 = <&pinctrl_uart3>;
415 #size-cells = <0>;
418 ethernet-phy@0 {
422 pinctrl-0 = <&pinctrl_fec0_phy_int>;
426 reg = <0>;
434 VF610_PAD_PTB2__GPIO_24 0x31c2
435 VF610_PAD_PTE27__GPIO_132 0x33e2
442 VF610_PAD_PTB1__GPIO_23 0x219d
448 VF610_PAD_PTA20__UART3_TX 0x21a2
449 VF610_PAD_PTA21__UART3_RX 0x21a1
455 VF610_PAD_PTA18__GPIO_8 0x31c2
456 VF610_PAD_PTA19__GPIO_9 0x31c2
457 VF610_PAD_PTB3__GPIO_25 0x31c2
463 VF610_PAD_PTB28__GPIO_98 0x219d