Lines Matching +full:0 +full:x21a2
20 reg = <0x80000000 0x10000000>;
25 #clock-cells = <0>;
37 pinctrl-0 = <&pinctrl_esdhc1>;
45 pinctrl-0 = <&pinctrl_fec1>;
53 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
54 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
55 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
56 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
57 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
58 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
59 VF610_PAD_PTB28__GPIO_98 0x219d
65 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
66 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
67 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
68 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
69 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
70 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
71 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
72 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
73 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
79 VF610_PAD_PTB4__UART1_TX 0x21a2
80 VF610_PAD_PTB5__UART1_RX 0x21a1
88 pinctrl-0 = <&pinctrl_uart1>;