Lines Matching +full:mdio +full:- +full:mux +full:- +full:mmioreg
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
7 /dts-v1/;
12 compatible = "fsl,ls1021a-qds", "fsl,ls1021a";
22 sys_mclk: clock-mclk {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <24576000>;
29 compatible = "regulator-fixed";
30 regulator-name = "3P3V";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
33 regulator-always-on;
37 compatible = "simple-audio-card";
38 simple-audio-card,format = "i2s";
39 simple-audio-card,widgets =
44 simple-audio-card,routing =
51 simple-audio-card,cpu {
52 sound-dai = <&sai2>;
53 frame-master;
54 bitclock-master;
57 simple-audio-card,codec {
58 sound-dai = <&codec>;
59 frame-master;
60 bitclock-master;
66 bus-num = <0>;
70 #address-cells = <1>;
71 #size-cells = <1>;
73 spi-max-frequency = <16000000>;
74 spi-cpol;
75 spi-cpha;
81 tbi-handle = <&tbi0>;
82 phy-handle = <&sgmii_phy1c>;
83 phy-connection-type = "sgmii";
88 tbi-handle = <&tbi0>;
89 phy-handle = <&sgmii_phy1d>;
90 phy-connection-type = "sgmii";
95 phy-handle = <&rgmii_phy3>;
96 phy-connection-type = "rgmii-id";
107 pca9547: mux@77 {
110 #address-cells = <1>;
111 #size-cells = <0>;
114 #address-cells = <1>;
115 #size-cells = <0>;
126 #address-cells = <1>;
127 #size-cells = <0>;
133 shunt-resistor = <1000>;
139 shunt-resistor = <1000>;
144 #address-cells = <1>;
145 #size-cells = <0>;
165 #address-cells = <1>;
166 #size-cells = <0>;
170 #sound-dai-cells = <0>;
173 VDDA-supply = <®_3p3v>;
174 VDDIO-supply = <®_3p3v>;
182 #address-cells = <2>;
183 #size-cells = <1>;
191 #address-cells = <1>;
192 #size-cells = <1>;
193 compatible = "cfi-flash";
195 big-endian;
196 bank-width = <2>;
197 device-width = <1>;
201 compatible = "fsl,ifc-nand";
205 fpga: board-control@3,0 {
206 #address-cells = <1>;
207 #size-cells = <1>;
208 compatible = "simple-mfd";
210 bank-width = <1>;
211 device-width = <1>;
214 mdio-mux-emi1 {
215 compatible = "mdio-mux-mmioreg";
216 mdio-parent-bus = <&mdio0>;
217 #address-cells = <1>;
218 #size-cells = <0>;
220 mux-mask = <0xe0>; /* EMI1[2:0] */
223 ls1021amdio0: mdio@0 {
225 #address-cells = <1>;
226 #size-cells = <0>;
227 rgmii_phy1: ethernet-phy@1 {
232 ls1021amdio1: mdio@20 {
234 #address-cells = <1>;
235 #size-cells = <0>;
236 rgmii_phy2: ethernet-phy@2 {
241 ls1021amdio2: mdio@40 {
243 #address-cells = <1>;
244 #size-cells = <0>;
245 rgmii_phy3: ethernet-phy@3 {
250 ls1021amdio3: mdio@60 {
252 #address-cells = <1>;
253 #size-cells = <0>;
254 sgmii_phy1c: ethernet-phy@1c {
259 ls1021amdio4: mdio@80 {
261 #address-cells = <1>;
262 #size-cells = <0>;
263 sgmii_phy1d: ethernet-phy@1d {
276 tbi0: tbi-phy@8 {
278 device_type = "tbi-phy";
286 compatible = "jedec,spi-nor";
287 #address-cells = <1>;
288 #size-cells = <1>;
289 spi-max-frequency = <20000000>;
291 spi-rx-bus-width = <4>;
292 spi-tx-bus-width = <4>;