Lines Matching +full:lpc3220 +full:- +full:clk
9 * Released under the terms of 3-clause BSD License
14 #include "../../armv7-m.dtsi"
16 #include "dt-bindings/clock/lpc18xx-cgu.h"
17 #include "dt-bindings/clock/lpc18xx-ccu.h"
23 #address-cells = <1>;
24 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
31 compatible = "arm,cortex-m3";
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <12000000>;
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <32768>;
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <0>;
55 clock-output-names = "enet_rx_clk";
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <0>;
62 clock-output-names = "enet_tx_clk";
66 compatible = "fixed-clock";
67 #clock-cells = <0>;
68 clock-frequency = <0>;
69 clock-output-names = "gp_clkin";
75 compatible = "nxp,lpc1850-sct-pwm";
78 clock-names = "pwm";
80 #pwm-cells = <3>;
84 dmac: dma-controller@40002000 {
86 arm,primecell-periphid = <0x00041080>;
90 clock-names = "apb_pclk";
92 #dma-cells = <2>;
93 dma-channels = <8>;
94 dma-requests = <16>;
95 lli-bus-interface-ahb1;
96 lli-bus-interface-ahb2;
97 mem-bus-interface-ahb1;
98 mem-bus-interface-ahb2;
99 memcpy-burst-size = <256>;
100 memcpy-bus-width = <32>;
103 spifi: flash-controller@40003000 {
104 compatible = "nxp,lpc1773-spifi";
106 reg-names = "spifi", "flash";
109 clock-names = "spifi", "reg";
115 compatible = "snps,dw-mshc";
119 clock-names = "ciu", "biu";
125 compatible = "nxp,lpc1850-ehci", "generic-ehci";
131 phy-names = "usb";
132 has-transaction-translator;
137 compatible = "nxp,lpc1850-ehci", "generic-ehci";
145 emc: memory-controller@40005000 {
149 clock-names = "mpmcclk", "apb_pclk";
151 #address-cells = <2>;
152 #size-cells = <1>;
160 lcdc: lcd-controller@40008000 {
164 interrupt-names = "combined";
166 clock-names = "clcdclk", "apb_pclk";
172 compatible = "nxp,lpc1857-eeprom";
174 reg-names = "reg", "mem";
176 clock-names = "eeprom";
183 compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
186 interrupt-names = "macirq";
188 clock-names = "stmmaceth";
190 reset-names = "stmmaceth";
191 rx-fifo-depth = <256>;
192 tx-fifo-depth = <256>;
199 compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
204 creg_clk: clock-controller {
205 compatible = "nxp,lpc1850-creg-clk";
207 #clock-cells = <1>;
211 compatible = "nxp,lpc1850-usb-otg-phy";
213 #phy-cells = <0>;
216 dmamux: dma-mux {
217 compatible = "nxp,lpc1850-dmamux";
218 #dma-cells = <3>;
219 dma-requests = <64>;
220 dma-masters = <&dmac>;
225 compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc";
229 clock-names = "rtc", "reg";
232 cgu: clock-controller@40050000 {
233 compatible = "nxp,lpc1850-cgu";
235 #clock-cells = <1>;
239 ccu1: clock-controller@40051000 {
240 compatible = "nxp,lpc1850-ccu";
242 #clock-cells = <1>;
247 clock-names = "base_apb3_clk", "base_apb1_clk",
253 ccu2: clock-controller@40052000 {
254 compatible = "nxp,lpc1850-ccu";
256 #clock-cells = <1>;
261 clock-names = "base_audio_clk", "base_uart3_clk",
267 rgu: reset-controller@40053000 {
268 compatible = "nxp,lpc1850-rgu";
271 clock-names = "delay", "reg";
272 #reset-cells = <1>;
276 compatible = "nxp,lpc1850-wwdt";
280 clock-names = "wdtclk", "reg";
284 compatible = "nxp,lpc1850-uart", "ns16550a";
286 reg-shift = <2>;
289 clock-names = "uartclk", "reg";
295 dma-names = "tx", "rx", "tx", "rx";
300 compatible = "nxp,lpc1850-uart", "ns16550a";
302 reg-shift = <2>;
305 clock-names = "uartclk", "reg";
309 dma-names = "tx", "rx";
318 clock-names = "sspclk", "apb_pclk";
322 dma-names = "rx", "tx";
323 #address-cells = <1>;
324 #size-cells = <0>;
329 compatible = "nxp,lpc3220-timer";
333 clock-names = "timerclk";
338 compatible = "nxp,lpc3220-timer";
342 clock-names = "timerclk";
347 compatible = "nxp,lpc1850-scu";
353 compatible = "nxp,lpc1788-i2c";
358 #address-cells = <1>;
359 #size-cells = <0>;
373 compatible = "nxp,lpc1850-uart", "ns16550a";
375 reg-shift = <2>;
378 clock-names = "uartclk", "reg";
382 dma-names = "tx", "rx";
387 compatible = "nxp,lpc1850-uart", "ns16550a";
389 reg-shift = <2>;
392 clock-names = "uartclk", "reg";
398 dma-names = "tx", "rx", "rx", "tx";
403 compatible = "nxp,lpc3220-timer";
407 clock-names = "timerclk";
412 compatible = "nxp,lpc3220-timer";
416 clock-names = "timerclk";
425 clock-names = "sspclk", "apb_pclk";
435 dma-names = "rx", "tx", "tx", "rx",
437 #address-cells = <1>;
438 #size-cells = <0>;
443 compatible = "nxp,lpc1788-i2c";
448 #address-cells = <1>;
449 #size-cells = <0>;
454 compatible = "nxp,lpc1850-dac";
472 compatible = "nxp,lpc1850-adc";
481 compatible = "nxp,lpc1850-adc";
490 compatible = "nxp,lpc1850-gpio";
493 gpio-controller;
494 #gpio-cells = <2>;
495 gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>,