Lines Matching full:scg1
132 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
186 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
223 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
224 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
237 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
238 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
247 scg1: clock-controller@403e0000 { label
248 compatible = "fsl,imx7ulp-scg1";
263 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
271 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
272 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
273 <&scg1 IMX7ULP_CLK_DDR_DIV>,
274 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
275 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
276 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
277 <&scg1 IMX7ULP_CLK_UPLL>,
278 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
279 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
280 <&scg1 IMX7ULP_CLK_ROSC>,
281 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
287 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
294 clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
295 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
303 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
304 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
305 <&scg1 IMX7ULP_CLK_DDR_DIV>,
306 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
307 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
308 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
309 <&scg1 IMX7ULP_CLK_UPLL>,
310 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
311 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
312 <&scg1 IMX7ULP_CLK_ROSC>,
313 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
333 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
336 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
346 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
349 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
361 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
373 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
461 clocks = <&scg1 IMX7ULP_CLK_DUMMY>;