Lines Matching +full:0 +full:x3000
12 reg = <0x80000000 0>; /* will be filled by U-Boot */
23 size = <0x4000000>;
35 pinctrl-0 = <&pinctrl_gpmi_nand>;
42 pinctrl-0 = <&pinctrl_i2c1>;
47 reg = <0x08>;
171 pinctrl-0 = <&pinctrl_uart1>;
179 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_wifibt_ctrl>;
190 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
191 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
192 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
193 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
194 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
195 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
196 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
197 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
198 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
199 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
200 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
201 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
202 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
203 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
204 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb0b1
210 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
211 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
217 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
218 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
219 MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x1b0b1
220 MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x1b0b1
226 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
227 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17051
228 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
229 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
230 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
231 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
237 MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x3000
238 MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x3000
239 MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x3000
240 MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x3000
241 MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x3000
242 MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x3000
248 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x08a0
249 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x08a0
255 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x3000
256 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3000