Lines Matching +full:phy +full:- +full:reset +full:- +full:duration
4 * This file is dual-licensed: you can use it either under the terms
41 #include <dt-bindings/gpio/gpio.h>
44 vcc_3v3: regulator-vcc-3v3 {
45 compatible = "regulator-fixed";
46 regulator-always-on;
47 regulator-name = "vcc_3v3";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
56 phy-mode = "rgmii-id";
59 * The PHY seems to require a long-enough reset duration to avoid
60 * some rare issues where the PHY gets stuck in an inconsistent and
61 * non-functional state at boot-up. 10ms proved to be fine .
63 phy-reset-duration = <10>;
64 phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
68 #address-cells = <1>;
69 #size-cells = <0>;
72 * The PHY can appear at either address 0 or 4 due to the
75 ethernet-phy@0 {
77 qca,clk-out-frequency = <125000000>;
78 qca,smarteee-tw-us-1g = <24>;
81 ethernet-phy@4 {
83 qca,clk-out-frequency = <125000000>;
84 qca,smarteee-tw-us-1g = <24>;
89 * will be enabled automatically by U-Boot if detected.
91 ethernet-phy@1 {
93 adi,phy-output-clock = "125mhz-free-running";
101 pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
105 /* AR8035 reset */
109 /* GPIO16 -> AR8035 25MHz */
117 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
135 * to high-z with the same pulls as above.
145 pinctrl_microsom_uart1: microsom-uart1 {
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_microsom_uart1>;