nxp/imx/imx6qdl-dhcom-drc02.dtsi

1 // SPDX-License-Identifier: GPL-2.0+
8 		stdout-path = "serial0:115200n8";
13  * Special SoM hardware required which uses the pins from micro SD card. The
14  * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
15  * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD
17  * pins, see uart1 and usdhc3 node below.
27 	 * during TX anyway and that it only controls drive enable DE
30 	rs485-rx-en-hog {
31 		gpio-hog;
33 		line-name = "rs485-rx-en";
34 		output-low;
39 	gpio-line-names =
43 		"", "", "", "DRC02-In1", "", "", "", "";
47 	gpio-line-names =
48 		"", "", "", "", "", "DHCOM-E", "DRC02-In2", "DHCOM-H",
49 		"DHCOM-I", "DRC02-HW0", "", "", "", "", "", "",
50 		"", "", "", "", "DRC02-Out1", "", "", "",
55 	gpio-line-names =
56 		"", "", "", "DRC02-Out2", "", "", "SOM-HW1", "",
57 		"", "", "", "", "", "", "DRC02-HW2", "DRC02-HW1",
72 	 * Due to the use of can2 the signals for can2 Tx and Rx are routed to
73 	 * DHCOM UART1 rts/cts pins. Therefore this UART have to use DHCOM GPIOs
76 	/delete-property/ uart-has-rtscts;
77 	cts-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; /* GPIO M */
78 	pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>;
79 	pinctrl-names = "default";
80 	rts-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
86 	 * controlled by DHCOM GPIO P. So remove rts/cts pins and the property
87 	 * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via
88 	 * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1
91 	/delete-property/ uart-has-rtscts;
92 	linux,rs485-enabled-at-boot-time;
93 	pinctrl-0 = <&pinctrl_uart5_core &pinctrl_dhcom_p &pinctrl_dhcom_q>;
94 	pinctrl-names = "default";
95 	rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */
99 	disable-over-current;
109 	 * disabled, because the pins SD3_DAT0 and SD3_DAT1 are muxed as
110 	 * can2 Tx and Rx.
116 	pinctrl-0 = <
122 			 * P: uart5 rs485-tx-en
123 			 * Q: uart5 rs485-rx-en
135 	pinctrl-names = "default";
137 	pinctrl_uart5_core: uart5-core-grp {
138 		fsl,pins = <