Lines Matching +full:port +full:- +full:endpoint
1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
24 operating-points = <
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
40 clock-latency = <61036>; /* two CLK32 periods */
41 #cooling-cells = <2>;
47 clock-names = "arm", "pll2_pfd2_396m", "step",
49 arm-supply = <®_arm>;
50 pu-supply = <®_pu>;
51 soc-supply = <®_soc>;
52 nvmem-cells = <&cpu_speed_grade>;
53 nvmem-cell-names = "speed_grade";
57 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
61 operating-points = <
69 fsl,soc-operating-points = <
70 /* ARM kHz SOC-PU uV */
77 clock-latency = <61036>; /* two CLK32 periods */
78 #cooling-cells = <2>;
84 clock-names = "arm", "pll2_pfd2_396m", "step",
86 arm-supply = <®_arm>;
87 pu-supply = <®_pu>;
88 soc-supply = <®_soc>;
92 compatible = "arm,cortex-a9";
95 next-level-cache = <&L2>;
96 operating-points = <
104 fsl,soc-operating-points = <
105 /* ARM kHz SOC-PU uV */
112 clock-latency = <61036>; /* two CLK32 periods */
113 #cooling-cells = <2>;
119 clock-names = "arm", "pll2_pfd2_396m", "step",
121 arm-supply = <®_arm>;
122 pu-supply = <®_pu>;
123 soc-supply = <®_soc>;
127 compatible = "arm,cortex-a9";
130 next-level-cache = <&L2>;
131 operating-points = <
139 fsl,soc-operating-points = <
140 /* ARM kHz SOC-PU uV */
147 clock-latency = <61036>; /* two CLK32 periods */
148 #cooling-cells = <2>;
154 clock-names = "arm", "pll2_pfd2_396m", "step",
156 arm-supply = <®_arm>;
157 pu-supply = <®_pu>;
158 soc-supply = <®_soc>;
164 compatible = "mmio-sram";
167 #address-cells = <1>;
168 #size-cells = <1>;
173 spba-bus@2000000 {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
182 clock-names = "ipg", "per";
184 dma-names = "rx", "tx";
191 compatible = "fsl,imx6q-ahci";
197 clock-names = "sata", "sata_ref", "ahb";
207 clock-names = "bus", "core";
208 power-domains = <&pd_pu>;
209 #cooling-cells = <2>;
213 #address-cells = <1>;
214 #size-cells = <0>;
215 compatible = "fsl,imx6q-ipu";
222 clock-names = "bus", "di0", "di1";
225 ipu2_csi0: port@0 {
228 ipu2_csi0_from_mipi_vc2: endpoint {
229 remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
233 ipu2_csi1: port@1 {
236 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
237 remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
241 ipu2_di0: port@2 {
242 #address-cells = <1>;
243 #size-cells = <0>;
246 ipu2_di0_disp0: endpoint@0 {
250 ipu2_di0_hdmi: endpoint@1 {
252 remote-endpoint = <&hdmi_mux_2>;
255 ipu2_di0_mipi: endpoint@2 {
257 remote-endpoint = <&mipi_mux_2>;
260 ipu2_di0_lvds0: endpoint@3 {
262 remote-endpoint = <&lvds0_mux_2>;
265 ipu2_di0_lvds1: endpoint@4 {
267 remote-endpoint = <&lvds1_mux_2>;
271 ipu2_di1: port@3 {
272 #address-cells = <1>;
273 #size-cells = <0>;
276 ipu2_di1_hdmi: endpoint@1 {
278 remote-endpoint = <&hdmi_mux_3>;
281 ipu2_di1_mipi: endpoint@2 {
283 remote-endpoint = <&mipi_mux_3>;
286 ipu2_di1_lvds0: endpoint@3 {
288 remote-endpoint = <&lvds0_mux_3>;
291 ipu2_di1_lvds1: endpoint@4 {
293 remote-endpoint = <&lvds1_mux_3>;
299 capture-subsystem {
300 compatible = "fsl,imx-capture-subsystem";
304 display-subsystem {
305 compatible = "fsl,imx-display-subsystem";
311 gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
320 gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
325 gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
329 gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
333 gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
338 gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
344 gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
349 compatible = "video-mux";
350 mux-controls = <&mux 0>;
351 #address-cells = <1>;
352 #size-cells = <0>;
354 port@0 {
357 ipu1_csi0_mux_from_mipi_vc0: endpoint {
358 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
362 port@1 {
365 ipu1_csi0_mux_from_parallel_sensor: endpoint {
369 port@2 {
372 ipu1_csi0_mux_to_ipu1_csi0: endpoint {
373 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
379 compatible = "video-mux";
380 mux-controls = <&mux 1>;
381 #address-cells = <1>;
382 #size-cells = <0>;
384 port@0 {
387 ipu2_csi1_mux_from_mipi_vc3: endpoint {
388 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
392 port@1 {
395 ipu2_csi1_mux_from_parallel_sensor: endpoint {
399 port@2 {
402 ipu2_csi1_mux_to_ipu2_csi1: endpoint {
403 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
410 compatible = "fsl,imx6q-hdmi";
413 port@2 {
416 hdmi_mux_2: endpoint {
417 remote-endpoint = <&ipu2_di0_hdmi>;
421 port@3 {
424 hdmi_mux_3: endpoint {
425 remote-endpoint = <&ipu2_di1_hdmi>;
432 compatible = "fsl,imx6q-iomuxc";
436 ipu1_csi1_from_mipi_vc1: endpoint {
437 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
446 clock-names = "di0_pll", "di1_pll",
450 lvds-channel@0 {
451 port@2 {
454 lvds0_mux_2: endpoint {
455 remote-endpoint = <&ipu2_di0_lvds0>;
459 port@3 {
462 lvds0_mux_3: endpoint {
463 remote-endpoint = <&ipu2_di1_lvds0>;
468 lvds-channel@1 {
469 port@2 {
472 lvds1_mux_2: endpoint {
473 remote-endpoint = <&ipu2_di0_lvds1>;
477 port@3 {
480 lvds1_mux_3: endpoint {
481 remote-endpoint = <&ipu2_di1_lvds1>;
488 port@1 {
491 mipi_vc0_to_ipu1_csi0_mux: endpoint {
492 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
496 port@2 {
499 mipi_vc1_to_ipu1_csi1: endpoint {
500 remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
504 port@3 {
507 mipi_vc2_to_ipu2_csi0: endpoint {
508 remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
512 port@4 {
515 mipi_vc3_to_ipu2_csi1_mux: endpoint {
516 remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
523 port@2 {
526 mipi_mux_2: endpoint {
527 remote-endpoint = <&ipu2_di0_mipi>;
531 port@3 {
534 mipi_mux_3: endpoint {
535 remote-endpoint = <&ipu2_di1_mipi>;
542 mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
552 compatible = "fsl,imx6q-vpu", "cnm,coda960";