Lines Matching +full:0 +full:x38
67 #size-cells = <0>;
69 port@0 {
70 reg = <0>;
90 pinctrl-0 = <&pinctrl_gpio_keys>;
103 pinctrl-0 = <&pinctrl_hpd>;
118 pinctrl-0 = <&pinctrl_i2c1mux>;
120 #size-cells = <0>;
125 i2c@0 {
126 reg = <0>;
128 #size-cells = <0>;
132 reg = <0x50>;
138 reg = <0x56>;
145 #size-cells = <0>;
152 #size-cells = <0>;
154 pinctrl-0 = <&pinctrl_ipu1>;
158 port@0 {
159 reg = <0>;
190 pinctrl-0 = <&pinctrl_hdmicec>;
197 pinctrl-0 = <&pinctrl_i2c1>;
203 pinctrl-0 = <&pinctrl_i2c2>;
210 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
216 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
222 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
228 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
229 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
235 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
241 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
242 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
248 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
249 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38
250 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38
251 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38
252 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38
253 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38
254 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
255 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38
256 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38
257 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38
258 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38
259 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38
260 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38
261 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38
262 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38
263 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38
264 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38
265 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38
266 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38
267 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38
268 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38
269 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38
270 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38
271 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38
272 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38
273 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38
274 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38
275 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38
281 MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1
282 MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1
283 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
284 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
290 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
291 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
292 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
293 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
294 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
295 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
301 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9
302 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9
303 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9
304 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9
305 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9
306 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9
312 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
313 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
314 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
315 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
316 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
317 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
327 pcie@0,0 {
328 reg = <0x000000 0 0 0 0>;
333 eth1: intel,i211@pcie0,0 {
334 reg = <0x010000 0 0 0 0>;
341 pinctrl-0 = <&pinctrl_uart2>;
348 pinctrl-0 = <&pinctrl_usdhc3>;