nxp/imx/imx6dl.dtsi

1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6dl-pinfunc.h"
15 		#address-cells = <1>;
16 		#size-cells = <0>;
19 			compatible = "arm,cortex-a9";
22 			next-level-cache = <&L2>;
23 			operating-points = <
29 			fsl,soc-operating-points = <
30 				/* ARM kHz  SOC-PU uV */
35 			clock-latency = <61036>; /* two CLK32 periods */
36 			#cooling-cells = <2>;
42 			clock-names = "arm", "pll2_pfd2_396m", "step",
44 			arm-supply = <&reg_arm>;
45 			pu-supply = <&reg_pu>;
46 			soc-supply = <&reg_soc>;
47 			nvmem-cells = <&cpu_speed_grade>;
48 			nvmem-cell-names = "speed_grade";
52 			compatible = "arm,cortex-a9";
55 			next-level-cache = <&L2>;
56 			operating-points = <
62 			fsl,soc-operating-points = <
63 				/* ARM kHz  SOC-PU uV */
68 			clock-latency = <61036>; /* two CLK32 periods */
69 			#cooling-cells = <2>;
75 			clock-names = "arm", "pll2_pfd2_396m", "step",
77 			arm-supply = <&reg_arm>;
78 			pu-supply = <&reg_pu>;
79 			soc-supply = <&reg_soc>;
85 			compatible = "mmio-sram";
88 			#address-cells = <1>;
89 			#size-cells = <1>;
107 				#address-cells = <1>;
108 				#size-cells = <0>;
109 				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
118 	capture-subsystem {
119 		compatible = "fsl,imx-capture-subsystem";
123 	display-subsystem {
124 		compatible = "fsl,imx-display-subsystem";
130 	gpio-ranges = <&iomuxc  0 131 2>, <&iomuxc  2 137 8>, <&iomuxc 10 189 2>,
140 	gpio-ranges = <&iomuxc  0 161 8>, <&iomuxc  8 208 8>, <&iomuxc 16  74 1>,
148 	gpio-ranges = <&iomuxc  0 97  2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
153 	gpio-ranges = <&iomuxc  5 136 1>, <&iomuxc  6 145 1>, <&iomuxc  7 150 1>,
161 	gpio-ranges = <&iomuxc  0 120 1>, <&iomuxc  2 77 1>, <&iomuxc  4 76 1>,
168 	gpio-ranges = <&iomuxc  0  23 6>, <&iomuxc  6  75 1>, <&iomuxc  7 156 1>,
177 	gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc  1 201 1>, <&iomuxc  2 196 1>,
184 		compatible = "video-mux";
185 		mux-controls = <&mux 0>;
186 		#address-cells = <1>;
187 		#size-cells = <0>;
193 				remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
201 				remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
209 				remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
217 				remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
232 				remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
238 		compatible = "video-mux";
239 		mux-controls = <&mux 1>;
240 		#address-cells = <1>;
241 		#size-cells = <0>;
247 				remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
255 				remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
263 				remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
271 				remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
286 				remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
292 &gpt {
293 	compatible = "fsl,imx6dl-gpt";
297 	compatible = "fsl,imx6dl-hdmi";
301 	compatible = "fsl,imx6dl-iomuxc";
306 		remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
314 	clock-names = "di0_pll", "di1_pll",
322 		#address-cells = <1>;
323 		#size-cells = <0>;
327 			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
332 			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
338 		#address-cells = <1>;
339 		#size-cells = <0>;
343 			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
348 			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
354 		#address-cells = <1>;
355 		#size-cells = <0>;
359 			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
364 			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
370 		#address-cells = <1>;
371 		#size-cells = <0>;
375 			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
380 			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
386 	mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
396 	compatible = "fsl,imx6dl-vpu", "cnm,coda960";