Lines Matching +full:0 +full:x0100000
16 reg = <0x10000000 0x40000000>;
29 #size-cells = <0>;
33 i2c5: i2c@0 {
34 reg = <0>;
36 #size-cells = <0>;
42 #size-cells = <0>;
49 pinctrl-0 = <&pinctrl_audmux>;
84 pinctrl-0 = <&pinctrl_spi1>;
87 flash@0 {
92 reg = <0>;
94 partition@0 {
96 reg = <0x0000000 0x100000>;
101 reg = <0x0100000 0x2fc000>;
106 reg = <0x03fc000 0x4000>;
114 pinctrl-0 = <&pinctrl_enet &pinctrl_phy_reset>;
122 #size-cells = <0>;
134 pinctrl-0 = <&pinctrl_i2c1>;
144 pinctrl-0 = <&pinctrl_i2c2>;
154 pinctrl-0 = <&pinctrl_i2c3>;
162 reg = <0x68>;
166 #clock-cells = <0>;
175 reg = <0x08>;
241 * maintain backward compatibility with hw-rev. A.0
273 reset-gpio = <&gpio1 20 0>;
278 pinctrl-0 = <&pinctrl_pwm4>;
299 pinctrl-0 = <&pinctrl_uart2>;
305 pinctrl-0 = <&pinctrl_uart3>;
317 pinctrl-0 = <&pinctrl_usbotg>;
323 pinctrl-0 = <&pinctrl_usdhc2>;
335 pinctrl-0 = <&pinctrl_usdhc3>;
347 pinctrl-0 = <&pinctrl_wdog>;
353 pinctrl-0 = <&pinctrl_hog>;
358 MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x110b0 /* Q7[67] HDA_SDO */
359 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x30b0 /* Q7[59] HDA_SYNC */
360 MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x30b0 /* Q7[65] HDA_SDI */
361 MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x30b0 /* Q7[63] HDA_BITCLK */
368 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
369 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
370 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
371 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
372 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
373 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
374 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
375 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
376 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
377 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
378 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
379 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
380 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
381 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
382 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
383 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
389 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* PCIE_WAKE_B */
390 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x80000000 /* I2C multiplexer */
391 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* SD4_CD# */
392 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* SD4_WP */
393 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x80000000 /* Camera MCLK */
399 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 /* Q7[66] I2C_CLK */
400 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 /* Q7[68] I2C_DAT */
406 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /* Q7[66] I2C_CLK */
407 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b0 /* Q7[68] I2C_DAT */
413 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 /* Q7[152] SDVO_CTRL_CLK */
414 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 /* Q7[150] SDVO_CTRL_DAT */
420 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 /* Q7[152] SDVO_CTRL_CLK */
421 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 /* Q7[150] SDVO_CTRL_DAT */
427 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 /* Q7[60] SMB_CLK */
428 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 /* Q7[62] SMB_DAT */
434 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 /* Q7[60] SMB_CLK */
435 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* Q7[62] SMB_DAT */
441 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* RGMII Phy Reset */
447 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 /* Q7[123] LVDS_BLT_CTRL */
453 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* Q7[112] LVDS_BLEN */
459 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* Q7[185] GPIO0 */
465 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* Q7[186] GPIO1 */
471 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* Q7[187] GPIO2 */
477 MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 /* Q7[188] GPIO3 */
483 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* Q7[189] GPIO4 */
489 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* Q7[190] GPIO5 */
495 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /* Q7[191] GPIO6 */
501 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* Q7[192] GPIO7 */
507 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 /* Q7[61] HDA_RST_N */
513 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* Q7[111] LVDS_PPEN */
519 MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 /* Q7[47] SDIO_PWR# */
525 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* Q7[21] SLP_BTN# */
531 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 /* Q7[202] SPI_CS1# */
538 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
539 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
540 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
541 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
548 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
549 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
555 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 /* Q7[177] UART0_RX */
556 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 /* Q7[171] UART0_TX */
562 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 /* Q7[92] USB_ID */
569 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
570 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
571 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
572 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
573 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
574 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
575 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2_CD */
582 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
583 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
584 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
585 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
586 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
587 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
588 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
589 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
590 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
591 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
597 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 /* Q7[45] SDIO_CMD */
598 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 /* Q7[42] SDIO_CLK */
599 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 /* Q7[48] SDIO_DAT1 */
600 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 /* Q7[49] SDIO_DAT0 */
601 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 /* Q7[50] SDIO_DAT3 */
602 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 /* Q7[51] SDIO_DAT2 */
608 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 /* Watchdog output signal */