Lines Matching +full:0 +full:x00000018
23 reg = <0x10000000 0x40000000>;
29 #clock-cells = <0>;
36 pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
48 pinctrl-0 = <&pinctrl_siox>;
58 pinctrl-0 = <&pinctrl_flexcan1>;
64 pinctrl-0 = <&pinctrl_flexcan2>;
77 pinctrl-0 = <&pinctrl_ecspi2>;
81 flash@0 {
83 reg = <0>;
90 pinctrl-0 = <&pinctrl_ecspi1>;
94 tpm@0 {
96 reg = <0>;
124 pinctrl-0 = <&pinctrl_i2c1>;
129 reg = <0x49>;
134 reg = <0x51>;
140 pinctrl-0 = <&pinctrl_hog>;
144 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00000018 /* buzzer */
145 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x00000018 /* OUT_1 */
146 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x00000018 /* OUT_2 */
147 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x00000018 /* OUT_3 */
148 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x00000000 /* In1 */
149 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x00000000 /* In2 */
150 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x00000018 /* unused watchdog pin */
151 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x00000018 /* unused watchdog pin */
158 MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x000100a0
159 MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x000100a0
160 MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x000100a0
161 MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000100a0
167 MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x000100b1
168 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x000100b1
169 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x000100b1
170 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000100b1
176 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
177 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x0001b098
178 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x0001b098
179 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098
180 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098
181 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098
182 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x0001b0b0
183 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x0001b0b0
184 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x0001b0b0
185 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x0001b0b0
186 MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x00000018
192 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x0001b020
193 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x0001b0b0
199 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x0001b020
200 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x0001b0b0
207 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b820
208 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b820
214 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x00000018
220 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0
226 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x0001b010 /* DIN */
227 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b010 /* DOUT */
228 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */
229 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x0001b010 /* DLD */
235 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x0001b010
236 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x0001b010
237 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x0001b010
238 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0001b010
239 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0001b010 /* DCD */
240 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0001b010 /* DTR */
241 MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0001b010 /* DSR */
247 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0001b010
248 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0001b010
249 MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0001b010
250 MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0001b010
251 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b010 /* DCD */
252 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b010 /* DTR */
253 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001b010 /* DSR */
259 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x0001b010
260 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x0001b010
266 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x0001b010
267 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x0001b010
268 MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x0001b010
274 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x0001b010
275 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0001b010
276 MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x0001b010 /* RTS */
282 MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0001b0b0
288 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x00017059
289 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x00010059
290 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x00017059
291 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x00017059
292 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x00017059
293 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x00017059
294 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x00017059
295 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x00017059
296 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x00017059
297 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x00017059
304 pinctrl-0 = <&pinctrl_enet>;
312 #size-cells = <0>;
323 pinctrl-0 = <&pinctrl_pcie>;
330 pinctrl-0 = <&pinctrl_uart1_dte>;
341 pinctrl-0 = <&pinctrl_uart2_dte>;
352 pinctrl-0 = <&pinctrl_uart3_dce>;
358 pinctrl-0 = <&pinctrl_uart4_dce>;
365 pinctrl-0 = <&pinctrl_uart5_dce>;
372 pinctrl-0 = <&pinctrl_usbh1>;
384 pinctrl-0 = <&pinctrl_usdhc3>;