Lines Matching +full:0 +full:x1f4
16 #size-cells = <0>;
18 port@0 {
19 reg = <0>;
41 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
42 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
43 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
44 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
45 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
51 MX53_PAD_EIM_A22__GPIO2_16 0x1f4
52 MX53_PAD_EIM_A21__GPIO2_17 0x1f4
53 MX53_PAD_EIM_A16__GPIO2_22 0x1f4
54 MX53_PAD_EIM_A18__GPIO2_20 0x1f4
61 pinctrl-0 = <&pinctrl_lvds0>;
64 lvds0: lvds-channel@0 {
65 reg = <0>;
85 pinctrl-0 = <&pinctrl_spi_gpio>;