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1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
6 #include "nuvoton-npcm750.dtsi"
7 #include "dt-bindings/gpio/gpio.h"
8 #include "nuvoton-npcm750-pincfg-evb.dtsi"
12 compatible = "nuvoton,npcm750-evb", "nuvoton,npcm750";
45 stdout-path = &serial3;
50 reg = <0x0 0x20000000>;
55 phy-mode = "rgmii-id";
60 phy-mode = "rgmii-id";
70 flash@0 {
71 compatible = "jedec,spi-nor";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 spi-rx-bus-width = <2>;
75 reg = <0>;
76 spi-max-frequency = <5000000>;
78 compatible = "fixed-partitions";
79 #address-cells = <1>;
80 #size-cells = <1>;
81 bbuboot1@0 {
82 label = "bb-uboot-1";
83 reg = <0x0000000 0x80000>;
84 read-only;
87 label = "bb-uboot-2";
88 reg = <0x0080000 0x80000>;
89 read-only;
92 label = "env-param";
93 reg = <0x0100000 0x40000>;
94 read-only;
98 reg = <0x0140000 0xC0000>;
102 reg = <0x0200000 0x400000>;
106 reg = <0x0600000 0x700000>;
110 reg = <0x0D00000 0x200000>;
114 reg = <0x0F00000 0x200000>;
118 reg = <0x1100000 0x200000>;
122 reg = <0x1300000 0x0>;
129 pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
131 flash@0 {
132 compatible = "jedec,spi-nor";
133 #address-cells = <1>;
134 #size-cells = <1>;
135 spi-rx-bus-width = <2>;
136 reg = <0>;
137 spi-max-frequency = <5000000>;
139 compatible = "fixed-partitions";
140 #address-cells = <1>;
141 #size-cells = <1>;
142 system1@0 {
143 label = "spi3-system1";
144 reg = <0x0 0x0>;
151 spix-mode;
183 kcs1: kcs1@0 {
187 kcs2: kcs2@0 {
191 kcs3: kcs3@0 {
198 clock-frequency = <100000>;
202 reg = <0x48>;
209 clock-frequency = <100000>;
211 temperature-sensor@48 {
213 reg = <0x48>;
220 clock-frequency = <100000>;
224 reg = <0x48>;
230 clock-frequency = <100000>;
235 clock-frequency = <100000>;
241 clock-frequency = <100000>;
245 reg = <0x48>;
251 clock-frequency = <100000>;
256 clock-frequency = <100000>;
261 clock-frequency = <100000>;
266 clock-frequency = <100000>;
271 clock-frequency = <100000>;
276 clock-frequency = <100000>;
282 fan@0 {
283 reg = <0x00>;
284 fan-tach-ch = /bits/ 8 <0x00 0x01>;
285 cooling-levels = <127 255>;
288 reg = <0x01>;
289 fan-tach-ch = /bits/ 8 <0x02 0x03>;
290 cooling-levels = /bits/ 8 <127 255>;
293 reg = <0x02>;
294 fan-tach-ch = /bits/ 8 <0x04 0x05>;
295 cooling-levels = /bits/ 8 <127 255>;
298 reg = <0x03>;
299 fan-tach-ch = /bits/ 8 <0x06 0x07>;
300 cooling-levels = /bits/ 8 <127 255>;
303 reg = <0x04>;
304 fan-tach-ch = /bits/ 8 <0x08 0x09>;
305 cooling-levels = /bits/ 8 <127 255>;
308 reg = <0x05>;
309 fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
310 cooling-levels = /bits/ 8 <127 255>;
313 reg = <0x06>;
314 fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
315 cooling-levels = /bits/ 8 <127 255>;
318 reg = <0x07>;
319 fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
320 cooling-levels = /bits/ 8 <127 255>;
325 cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
327 flash@0 {
329 "jedec,spi-nor";
330 reg = <0x0>;
331 #address-cells = <1>;
332 #size-cells = <1>;
333 spi-max-frequency = <5000000>;
334 partition@0 {
336 reg = <0x0000000 0x800000>;
340 reg = <0x800000 0x0>;
346 cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
348 flash@0 {
350 "jedec,spi-nor";
351 reg = <0x0>;
352 #address-cells = <1>;
353 #size-cells = <1>;
354 spi-max-frequency = <5000000>;
355 partition@0 {
357 reg = <0x0000000 0x800000>;
361 reg = <0x800000 0x0>;
367 pinctrl-names = "default";
368 pinctrl-0 = < &iox1_pins