Lines Matching +full:0 +full:xf0008000
37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x00300000 0x100000>;
68 ranges = <0 0x00300000 0x100000>;
79 #size-cells = <0>;
81 reg = <0x00500000 0x100000
82 0xf803c000 0x400>;
93 reg = <0x00600000 0x100000>;
102 reg = <0x00700000 0x100000>;
117 reg = <0x10000000 0x60000000>;
118 ranges = <0x0 0x0 0x10000000 0x10000000
119 0x1 0x0 0x20000000 0x10000000
120 0x2 0x0 0x30000000 0x10000000
121 0x3 0x0 0x40000000 0x10000000
122 0x4 0x0 0x50000000 0x10000000
123 0x5 0x0 0x60000000 0x10000000>;
139 reg = <0x80000000 0x300>;
140 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
150 reg = <0x90000000 0x300>;
151 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
167 reg = <0xf0000000 0x200>;
171 ranges = <0x0 0xf0000000 0x800>;
176 reg = <0x200 0x200>;
179 (AT91_XDMAC_DT_MEM_IF(0) |
183 (AT91_XDMAC_DT_MEM_IF(0) |
197 reg = <0x400 0x200>;
202 (AT91_XDMAC_DT_MEM_IF(0) |
206 (AT91_XDMAC_DT_MEM_IF(0) |
216 reg = <0x600 0x200>;
219 #size-cells = <0>;
222 (AT91_XDMAC_DT_MEM_IF(0) |
226 (AT91_XDMAC_DT_MEM_IF(0) |
237 reg = <0xf0004000 0x200>;
241 ranges = <0x0 0xf0004000 0x800>;
246 reg = <0x200 0x200>;
250 (AT91_XDMAC_DT_MEM_IF(0) |
254 (AT91_XDMAC_DT_MEM_IF(0) |
268 reg = <0x400 0x200>;
273 (AT91_XDMAC_DT_MEM_IF(0) |
277 (AT91_XDMAC_DT_MEM_IF(0) |
287 reg = <0x600 0x200>;
290 #size-cells = <0>;
293 (AT91_XDMAC_DT_MEM_IF(0) |
297 (AT91_XDMAC_DT_MEM_IF(0) |
308 reg = <0xf0008000 0x1000>;
309 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
317 reg = <0xf0010000 0x4000>;
320 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
323 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
333 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
337 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
340 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
347 #size-cells = <0>;
353 reg = <0xf001c000 0x100>;
356 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
359 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
369 reg = <0xf0020000 0x200>;
373 ranges = <0x0 0xf0020000 0x800>;
378 reg = <0x200 0x200>;
381 (AT91_XDMAC_DT_MEM_IF(0) |
385 (AT91_XDMAC_DT_MEM_IF(0) |
399 reg = <0x600 0x200>;
402 #size-cells = <0>;
405 (AT91_XDMAC_DT_MEM_IF(0) |
409 (AT91_XDMAC_DT_MEM_IF(0) |
420 reg = <0xf0024000 0x200>;
424 ranges = <0x0 0xf0024000 0x800>;
429 reg = <0x200 0x200>;
432 (AT91_XDMAC_DT_MEM_IF(0) |
436 (AT91_XDMAC_DT_MEM_IF(0) |
450 reg = <0x600 0x200>;
453 #size-cells = <0>;
456 (AT91_XDMAC_DT_MEM_IF(0) |
460 (AT91_XDMAC_DT_MEM_IF(0) |
471 reg = <0xf0028000 0x100>;
479 reg = <0xf002c000 0x100>;
480 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
482 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
491 reg = <0xf0030000 0x100>;
492 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
498 reg = <0xf0034000 0x100>;
499 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
501 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
504 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
513 reg = <0xf0038000 0x100>;
514 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
516 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
519 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
528 reg = <0xf003c000 0x100>;
531 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
541 reg = <0xf8000000 0x300>;
550 reg = <0xf8004000 0x300>;
560 #size-cells = <0>;
561 reg = <0xf8008000 0x100>;
562 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
563 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
570 #size-cells = <0>;
571 reg = <0xf800c000 0x100>;
572 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
573 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
579 reg = <0xf8010000 0x200>;
583 ranges = <0x0 0xf8010000 0x800>;
588 reg = <0x200 0x200>;
591 (AT91_XDMAC_DT_MEM_IF(0) |
595 (AT91_XDMAC_DT_MEM_IF(0) |
609 reg = <0x600 0x200>;
612 #size-cells = <0>;
615 (AT91_XDMAC_DT_MEM_IF(0) |
619 (AT91_XDMAC_DT_MEM_IF(0) |
630 reg = <0xf8014000 0x200>;
634 ranges = <0x0 0xf8014000 0x800>;
639 reg = <0x200 0x200>;
642 (AT91_XDMAC_DT_MEM_IF(0) |
646 (AT91_XDMAC_DT_MEM_IF(0) |
660 reg = <0x600 0x200>;
663 #size-cells = <0>;
666 (AT91_XDMAC_DT_MEM_IF(0) |
670 (AT91_XDMAC_DT_MEM_IF(0) |
681 reg = <0xf8018000 0x200>;
685 ranges = <0x0 0xf8018000 0x800>;
690 reg = <0x200 0x200>;
693 (AT91_XDMAC_DT_MEM_IF(0) |
697 (AT91_XDMAC_DT_MEM_IF(0) |
711 reg = <0x600 0x200>;
714 #size-cells = <0>;
717 (AT91_XDMAC_DT_MEM_IF(0) |
721 (AT91_XDMAC_DT_MEM_IF(0) |
732 reg = <0xf801c000 0x200>;
736 ranges = <0x0 0xf801c000 0x800>;
741 reg = <0x200 0x200>;
744 (AT91_XDMAC_DT_MEM_IF(0) |
746 AT91_XDMAC_DT_PERID(0))>,
748 (AT91_XDMAC_DT_MEM_IF(0) |
762 reg = <0x400 0x200>;
767 (AT91_XDMAC_DT_MEM_IF(0) |
769 AT91_XDMAC_DT_PERID(0))>,
771 (AT91_XDMAC_DT_MEM_IF(0) |
781 reg = <0x600 0x200>;
784 #size-cells = <0>;
787 (AT91_XDMAC_DT_MEM_IF(0) |
789 AT91_XDMAC_DT_PERID(0))>,
791 (AT91_XDMAC_DT_MEM_IF(0) |
802 reg = <0xf8020000 0x200>;
806 ranges = <0x0 0xf8020000 0x800>;
811 reg = <0x200 0x200>;
814 (AT91_XDMAC_DT_MEM_IF(0) |
818 (AT91_XDMAC_DT_MEM_IF(0) |
832 reg = <0x400 0x200>;
837 (AT91_XDMAC_DT_MEM_IF(0) |
841 (AT91_XDMAC_DT_MEM_IF(0) |
851 reg = <0x600 0x200>;
854 #size-cells = <0>;
857 (AT91_XDMAC_DT_MEM_IF(0) |
861 (AT91_XDMAC_DT_MEM_IF(0) |
872 reg = <0xf8024000 0x200>;
876 ranges = <0x0 0xf8024000 0x800>;
881 reg = <0x200 0x200>;
884 (AT91_XDMAC_DT_MEM_IF(0) |
888 (AT91_XDMAC_DT_MEM_IF(0) |
902 reg = <0x400 0x200>;
907 (AT91_XDMAC_DT_MEM_IF(0) |
911 (AT91_XDMAC_DT_MEM_IF(0) |
921 reg = <0x600 0x200>;
924 #size-cells = <0>;
927 (AT91_XDMAC_DT_MEM_IF(0) |
931 (AT91_XDMAC_DT_MEM_IF(0) |
942 reg = <0xf8028000 0x200>;
946 ranges = <0x0 0xf8028000 0x800>;
951 reg = <0x200 0x200>;
954 (AT91_XDMAC_DT_MEM_IF(0) |
958 (AT91_XDMAC_DT_MEM_IF(0) |
972 reg = <0x400 0x200>;
977 (AT91_XDMAC_DT_MEM_IF(0) |
981 (AT91_XDMAC_DT_MEM_IF(0) |
991 reg = <0x600 0x200>;
994 #size-cells = <0>;
997 (AT91_XDMAC_DT_MEM_IF(0) |
1001 (AT91_XDMAC_DT_MEM_IF(0) |
1012 reg = <0xf802c000 0x1000>;
1021 reg = <0xf8030000 0x1000>;
1030 reg = <0xf8034000 0x300>;
1039 reg = <0xf8038000 0x4000>;
1040 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
1050 #size-cells = <0>;
1052 port@0 {
1054 #size-cells = <0>;
1055 reg = <0>;
1067 reg = <0xf8040000 0x200>;
1071 ranges = <0x0 0xf8040000 0x800>;
1076 reg = <0x200 0x200>;
1079 (AT91_XDMAC_DT_MEM_IF(0) |
1083 (AT91_XDMAC_DT_MEM_IF(0) |
1097 reg = <0x600 0x200>;
1100 #size-cells = <0>;
1103 (AT91_XDMAC_DT_MEM_IF(0) |
1107 (AT91_XDMAC_DT_MEM_IF(0) |
1118 reg = <0xf8044000 0x200>;
1122 ranges = <0x0 0xf8044000 0x800>;
1127 reg = <0x200 0x200>;
1130 (AT91_XDMAC_DT_MEM_IF(0) |
1134 (AT91_XDMAC_DT_MEM_IF(0) |
1148 reg = <0x600 0x200>;
1151 #size-cells = <0>;
1154 (AT91_XDMAC_DT_MEM_IF(0) |
1158 (AT91_XDMAC_DT_MEM_IF(0) |
1169 reg = <0xf8048000 0x100>;
1176 #size-cells = <0>;
1182 reg = <0xf804c000 0x100>;
1186 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
1198 reg = <0xf8050000 0x100>;
1203 reg = <0xffffde00 0x200>;
1208 reg = <0xffffe000 0x300>,
1209 <0xffffe600 0x100>;
1214 reg = <0xffffe800 0x200>;
1221 reg = <0xffffea00 0x100>;
1228 reg = <0xfffff100 0x100>;
1234 reg = <0xfffff200 0x200>;
1238 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1241 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1253 ranges = <0xfffff400 0xfffff400 0x800>;
1258 0xffffffff 0xffe03fff 0xef00019d /* pioA */
1259 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */
1260 0xffffffff 0xffffffff 0xf83fffff /* pioC */
1261 0x003fffff 0x003f8000 0x00000000 /* pioD */
1266 reg = <0xfffff400 0x200>;
1277 reg = <0xfffff600 0x200>;
1289 reg = <0xfffff800 0x200>;
1300 reg = <0xfffffa00 0x200>;
1313 reg = <0xfffffc00 0x200>;
1316 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
1322 reg = <0xfffffe00 0x10>;
1323 clocks = <&clk32k 0>;
1328 reg = <0xfffffe10 0x10>;
1329 clocks = <&clk32k 0>;
1331 #size-cells = <0>;
1339 reg = <0xfffffe20 0x20>;
1346 reg = <0xfffffe40 0x10>;
1353 reg = <0xfffffe50 0x4>;
1360 reg = <0xfffffe60 0x10>;
1365 reg = <0xfffffea8 0x100>;
1372 reg = <0xffffff80 0x24>;
1374 clocks = <&clk32k 0>;