dts/microchip/lan966x-pcb8290.dts

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3  * lan966x-pcb8290.dts - Device Tree file for LAN966X-PCB8290 board
9 /dts-v1/;
10 #include "lan966x.dtsi"
11 #include "dt-bindings/phy/phy-lan966x-serdes.h"
15 	compatible = "microchip,lan9668-pcb8290", "microchip,lan9668", "microchip,lan966";
17 	gpio-restart {
18 		compatible = "gpio-restart";
29 	miim_a_pins: mdio-pins {
35 	pps_out_pins: pps-out-pins {
41 	ptp_ext_pins: ptp-ext-pins {
47 	udc_pins: ucd-pins {
55 	pinctrl-0 = <&miim_a_pins>;
56 	pinctrl-names = "default";
59 	ext_phy0: ethernet-phy@7 {
62 		interrupt-parent = <&gpio>;
63 		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
66 	ext_phy1: ethernet-phy@8 {
69 		interrupt-parent = <&gpio>;
70 		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
73 	ext_phy2: ethernet-phy@9 {
76 		interrupt-parent = <&gpio>;
77 		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
80 	ext_phy3: ethernet-phy@10 {
83 		interrupt-parent = <&gpio>;
84 		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
87 	ext_phy4: ethernet-phy@15 {
90 		interrupt-parent = <&gpio>;
91 		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
94 	ext_phy5: ethernet-phy@16 {
97 		interrupt-parent = <&gpio>;
98 		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
101 	ext_phy6: ethernet-phy@17 {
104 		interrupt-parent = <&gpio>;
105 		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
108 	ext_phy7: ethernet-phy@18 {
111 		interrupt-parent = <&gpio>;
112 		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
118 	phy-handle = <&ext_phy2>;
119 	phy-mode = "qsgmii";
120 	phys = <&serdes 0 SERDES6G(1)>;
126 	phy-handle = <&ext_phy3>;
127 	phy-mode = "qsgmii";
128 	phys = <&serdes 1 SERDES6G(1)>;
134 	phy-handle = <&ext_phy0>;
135 	phy-mode = "qsgmii";
136 	phys = <&serdes 2 SERDES6G(1)>;
142 	phy-handle = <&ext_phy1>;
143 	phy-mode = "qsgmii";
144 	phys = <&serdes 3 SERDES6G(1)>;
150 	phy-handle = <&ext_phy6>;
151 	phy-mode = "qsgmii";
152 	phys = <&serdes 4 SERDES6G(2)>;
158 	phy-handle = <&ext_phy7>;
159 	phy-mode = "qsgmii";
160 	phys = <&serdes 5 SERDES6G(2)>;
166 	phy-handle = <&ext_phy4>;
167 	phy-mode = "qsgmii";
168 	phys = <&serdes 6 SERDES6G(2)>;
174 	phy-handle = <&ext_phy5>;
175 	phy-mode = "qsgmii";
176 	phys = <&serdes 7 SERDES6G(2)>;
180 &serdes {
185 	pinctrl-0 = <&pps_out_pins>, <&ptp_ext_pins>;
186 	pinctrl-names = "default";
191 	pinctrl-0 = <&udc_pins>;
192 	pinctrl-names = "default";
193 	atmel,vbus-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;