Lines Matching +full:0 +full:xfffc4000
44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
55 reg = <0x20000000 0x04000000>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
74 reg = <0x00200000 0x4000>;
77 ranges = <0 0x00200000 0x4000>;
96 reg = <0xfffff000 0x200>;
102 reg = <0xffffff00 0x100>;
107 reg = <0xfffffc00 0x100>;
116 reg = <0xfffffd00 0x100>;
127 reg = <0xfffffe00 0x40>;
136 #size-cells = <0>;
137 reg = <0xfffa0000 0x100>;
138 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
139 <18 IRQ_TYPE_LEVEL_HIGH 0>,
140 <19 IRQ_TYPE_LEVEL_HIGH 0>;
148 #size-cells = <0>;
149 reg = <0xfffa4000 0x100>;
150 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>,
151 <21 IRQ_TYPE_LEVEL_HIGH 0>,
152 <22 IRQ_TYPE_LEVEL_HIGH 0>;
159 reg = <0xfffb8000 0x4000>;
162 pinctrl-0 = <&pinctrl_twi>;
165 #size-cells = <0>;
171 reg = <0xfffb4000 0x4000>;
172 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
176 #size-cells = <0>;
182 reg = <0xfffd0000 0x4000>;
185 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
193 reg = <0xfffd4000 0x4000>;
196 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
204 reg = <0xfffd8000 0x4000>;
207 pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
215 reg = <0xfffbc000 0x4000>;
219 pinctrl-0 = <&pinctrl_macb_rmii>;
229 ranges = <0xfffff400 0xfffff400 0x800>;
233 0xffffffff 0xffffffff /* pioA */
234 0xffffffff 0x083fffff /* pioB */
235 0xffff3fff 0x00000000 /* pioC */
236 0x03ff87ff 0x0fffff80 /* pioD */
241 pinctrl_dbgu: dbgu-0 {
249 pinctrl_uart0: uart0-0 {
255 pinctrl_uart0_cts: uart0_cts-0 {
260 pinctrl_uart0_rts: uart0_rts-0 {
267 pinctrl_uart1: uart1-0 {
273 pinctrl_uart1_rts: uart1_rts-0 {
278 pinctrl_uart1_cts: uart1_cts-0 {
283 pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
289 pinctrl_uart1_dcd: uart1_dcd-0 {
294 pinctrl_uart1_ri: uart1_ri-0 {
301 pinctrl_uart2: uart2-0 {
307 pinctrl_uart2_rts: uart2_rts-0 {
312 pinctrl_uart2_cts: uart2_cts-0 {
319 pinctrl_uart3: uart3-0 {
325 pinctrl_uart3_rts: uart3_rts-0 {
327 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
330 pinctrl_uart3_cts: uart3_cts-0 {
337 pinctrl_nand: nand-0 {
345 pinctrl_macb_rmii: macb_rmii-0 {
359 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
373 pinctrl_mmc0_clk: mmc0_clk-0 {
378 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
384 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
391 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
397 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
406 pinctrl_ssc0_tx: ssc0_tx-0 {
408 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
413 pinctrl_ssc0_rx: ssc0_rx-0 {
422 pinctrl_ssc1_tx: ssc1_tx-0 {
429 pinctrl_ssc1_rx: ssc1_rx-0 {
438 pinctrl_ssc2_tx: ssc2_tx-0 {
445 pinctrl_ssc2_rx: ssc2_rx-0 {
454 pinctrl_twi: twi-0 {
460 pinctrl_twi_gpio: twi_gpio-0 {
468 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
472 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
476 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
480 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
484 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
488 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
492 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
496 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
500 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
506 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
510 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
514 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
518 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
522 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
526 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
530 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
534 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
538 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
544 pinctrl_spi0: spi0-0 {
546 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
554 reg = <0xfffff400 0x200>;
565 reg = <0xfffff600 0x200>;
576 reg = <0xfffff800 0x200>;
587 reg = <0xfffffa00 0x200>;
599 reg = <0xfffff200 0x200>;
603 pinctrl-0 = <&pinctrl_dbgu>;
611 reg = <0xfffc0000 0x200>;
617 pinctrl-0 = <&pinctrl_uart0>;
625 reg = <0xfffc4000 0x200>;
631 pinctrl-0 = <&pinctrl_uart1>;
639 reg = <0xfffc8000 0x200>;
645 pinctrl-0 = <&pinctrl_uart2>;
653 reg = <0xfffcc000 0x200>;
659 pinctrl-0 = <&pinctrl_uart3>;
667 reg = <0xfffb0000 0x4000>;
676 #size-cells = <0>;
678 reg = <0xfffe0000 0x200>;
681 pinctrl-0 = <&pinctrl_spi0>;
692 reg = <0x40000000 0x10000000>;
696 pinctrl-0 = <&pinctrl_nand>;
699 0
707 reg = <0x00300000 0x100000>;
715 i2c-gpio-0 {
724 pinctrl-0 = <&pinctrl_twi_gpio>;
726 #size-cells = <0>;