Lines Matching refs:pericfg
243 pericfg: syscon@10003000 { label
244 compatible = "mediatek,mt7623-pericfg",
245 "mediatek,mt2701-pericfg",
370 clocks = <&pericfg CLK_PERI_AUXADC>;
380 clocks = <&pericfg CLK_PERI_UART0_SEL>,
381 <&pericfg CLK_PERI_UART0>;
391 clocks = <&pericfg CLK_PERI_UART1_SEL>,
392 <&pericfg CLK_PERI_UART1>;
402 clocks = <&pericfg CLK_PERI_UART2_SEL>,
403 <&pericfg CLK_PERI_UART2>;
413 clocks = <&pericfg CLK_PERI_UART3_SEL>,
414 <&pericfg CLK_PERI_UART3>;
424 <&pericfg CLK_PERI_PWM>,
425 <&pericfg CLK_PERI_PWM1>,
426 <&pericfg CLK_PERI_PWM2>,
427 <&pericfg CLK_PERI_PWM3>,
428 <&pericfg CLK_PERI_PWM4>,
429 <&pericfg CLK_PERI_PWM5>;
442 clocks = <&pericfg CLK_PERI_I2C0>,
443 <&pericfg CLK_PERI_AP_DMA>;
457 clocks = <&pericfg CLK_PERI_I2C1>,
458 <&pericfg CLK_PERI_AP_DMA>;
472 clocks = <&pericfg CLK_PERI_I2C2>,
473 <&pericfg CLK_PERI_AP_DMA>;
489 <&pericfg CLK_PERI_SPI0>;
500 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
502 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
515 clocks = <&pericfg CLK_PERI_BTIF>;
528 clocks = <&pericfg CLK_PERI_NFI>,
529 <&pericfg CLK_PERI_NFI_PAD>;
542 clocks = <&pericfg CLK_PERI_NFI_ECC>;
551 clocks = <&pericfg CLK_PERI_FLASH>,
568 <&pericfg CLK_PERI_SPI1>;
582 <&pericfg CLK_PERI_SPI2>;
595 clocks = <&pericfg CLK_PERI_USB0>,
596 <&pericfg CLK_PERI_USB0_MCU>,
597 <&pericfg CLK_PERI_USB_SLV>;
720 clocks = <&pericfg CLK_PERI_MSDC30_0>,
731 clocks = <&pericfg CLK_PERI_MSDC30_1>,