Lines Matching +full:0 +full:x10600
24 reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
25 ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
28 clocks = <&core_clk 0>;
34 reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
35 ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
38 clocks = <&core_clk 0>;
44 reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
45 ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
48 clocks = <&core_clk 0>;
54 reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
55 ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>;
58 clocks = <&core_clk 0>;
66 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
72 reg = <0x10100 0x40>;
82 #size-cells = <0>;
83 cell-index = <0>;
84 reg = <0x10600 0x28>;
90 reg = <0x11000 0x20>;
92 #size-cells = <0>;
94 clocks = <&core_clk 0>;
100 reg = <0x12000 0x100>;
103 clocks = <&core_clk 0>;
109 reg = <0x12100 0x100>;
112 clocks = <&core_clk 0>;
120 reg = <0x20110 0x8>;
121 interrupts = <0>;
129 reg = <0x20200 0x08>;
134 reg = <0x20300 0x20>;
137 clocks = <&core_clk 0>;
142 reg = <0x20300 0x28>, <0x20108 0x4>;
145 clocks = <&core_clk 0>;
151 reg = <0x50000 0x1000>;
158 reg = <0x60900 0x100
159 0x60b00 0x100>;
178 #size-cells = <0>;
179 reg = <0x72000 0x4000>;
183 ethport: ethernet-port@0 {
185 reg = <0>;
196 #size-cells = <0>;
197 reg = <0x72004 0x84>;
206 reg = <0x80000 0x5000>;
213 reg = <0x90000 0x10000>;
217 marvell,crypto-sram-size = <0x800>;
223 reg = <0xa0000 0x1000>;
231 reg = <MBUS_ID(0x09, 0x00) 0x0 0x800>;