dts/marvell/mmp3.dtsi

198 				clocks = <&soc_clocks MMP2_CLK_USB>;
216 				clocks = <&soc_clocks MMP2_CLK_USBHSIC0>;
237 				clocks = <&soc_clocks MMP2_CLK_USBHSIC1>;
250 				clocks = <&soc_clocks MMP2_CLK_SDH0>;
259 				clocks = <&soc_clocks MMP2_CLK_SDH1>;
268 				clocks = <&soc_clocks MMP2_CLK_SDH2>;
277 				clocks = <&soc_clocks MMP2_CLK_SDH3>;
286 				clocks = <&soc_clocks MMP3_CLK_SDH4>;
298 				clocks = <&soc_clocks MMP2_CLK_CCIC0>;
300 				power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
311 				clocks = <&soc_clocks MMP2_CLK_CCIC1>;
313 				power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
325 				clocks = <&soc_clocks MMP3_CLK_GPU_3D>,
326 					 <&soc_clocks MMP3_CLK_GPU_BUS>;
328 				power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
337 				clocks = <&soc_clocks MMP3_CLK_GPU_2D>,
338 					 <&soc_clocks MMP3_CLK_GPU_BUS>;
340 				power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
355 				clocks = <&soc_clocks MMP2_CLK_TIMER>;
362 				clocks = <&soc_clocks MMP2_CLK_UART0>;
363 				resets = <&soc_clocks MMP2_CLK_UART0>;
372 				clocks = <&soc_clocks MMP2_CLK_UART1>;
373 				resets = <&soc_clocks MMP2_CLK_UART1>;
382 				clocks = <&soc_clocks MMP2_CLK_UART2>;
383 				resets = <&soc_clocks MMP2_CLK_UART2>;
392 				clocks = <&soc_clocks MMP2_CLK_UART3>;
393 				resets = <&soc_clocks MMP2_CLK_UART3>;
407 				clocks = <&soc_clocks MMP2_CLK_GPIO>;
408 				resets = <&soc_clocks MMP2_CLK_GPIO>;
442 				clocks = <&soc_clocks MMP2_CLK_TWSI0>;
443 				resets = <&soc_clocks MMP2_CLK_TWSI0>;
455 				clocks = <&soc_clocks MMP2_CLK_TWSI1>;
456 				resets = <&soc_clocks MMP2_CLK_TWSI1>;
467 				clocks = <&soc_clocks MMP2_CLK_TWSI2>;
468 				resets = <&soc_clocks MMP2_CLK_TWSI2>;
479 				clocks = <&soc_clocks MMP2_CLK_TWSI3>;
480 				resets = <&soc_clocks MMP2_CLK_TWSI3>;
492 				clocks = <&soc_clocks MMP2_CLK_TWSI4>;
493 				resets = <&soc_clocks MMP2_CLK_TWSI4>;
504 				clocks = <&soc_clocks MMP2_CLK_TWSI5>;
505 				resets = <&soc_clocks MMP2_CLK_TWSI5>;
517 				clocks = <&soc_clocks MMP2_CLK_RTC>;
518 				resets = <&soc_clocks MMP2_CLK_RTC>;
525 				clocks = <&soc_clocks MMP2_CLK_SSP0>;
535 				clocks = <&soc_clocks MMP2_CLK_SSP1>;
545 				clocks = <&soc_clocks MMP2_CLK_SSP2>;
555 				clocks = <&soc_clocks MMP2_CLK_SSP3>;
570 		soc_clocks: clocks@d4050000 {  label