Lines Matching +full:0 +full:x0100000
15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
37 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
38 MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
39 MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
42 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
43 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
48 cle = <0>;
52 reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
56 pinctrl-0 = <&pmx_nand>;
63 reg = <MBUS_ID(0x03, 0x01) 0x0 0x800>;
72 ranges = <0x00000000 0xf1000000 0x0100000>;
78 reg = <0x10000 0x20>;
124 reg = <0x10030 0x4>;
131 #size-cells = <0>;
132 cell-index = <0>;
134 reg = <0x10600 0x28>;
136 pinctrl-0 = <&pmx_spi>;
145 reg = <0x10100 0x40>;
157 reg = <0x10140 0x40>;
167 reg = <0x11000 0x20>;
169 #size-cells = <0>;
173 pinctrl-0 = <&pmx_twsi0>;
180 reg = <0x12000 0x100>;
184 pinctrl-0 = <&pmx_uart0>;
191 reg = <0x12100 0x100>;
195 pinctrl-0 = <&pmx_uart1>;
202 reg = <0x20000 0x80>, <0x1500 0x20>;
207 reg = <0x20000 0x120>;
214 reg = <0x20110 0x8>;
221 reg = <0x2011c 0x4>;
222 clocks = <&core_clk 0>;
228 reg = <0x20128 0x4>;
235 reg = <0x20200 0x10>, <0x20210 0x10>;
240 reg = <0x20300 0x20>;
243 clocks = <&core_clk 0>;
248 reg = <0x20300 0x28>, <0x20108 0x4>;
257 reg = <0x30000 0x10000>;
262 marvell,crypto-sram-size = <0x800>;
268 reg = <0x50000 0x1000>;
276 reg = <0x60800 0x100
277 0x60A00 0x100>;
296 reg = <0x60900 0x100
297 0x60B00 0x100>;
317 #size-cells = <0>;
318 reg = <0x72000 0x4000>;
319 clocks = <&gate_clk 0>;
323 eth0port: ethernet0-port@0 {
325 reg = <0>;
336 #size-cells = <0>;
337 reg = <0x72004 0x84>;
339 clocks = <&gate_clk 0>;
348 #size-cells = <0>;
349 reg = <0x76000 0x4000>;
352 pinctrl-0 = <&pmx_ge1>;
356 eth1port: ethernet1-port@0 {
358 reg = <0>;
368 reg = <0x82000 0x0334>;
371 #phy-cells = <0>;
377 reg = <0x84000 0x0334>;
380 #phy-cells = <0>;
386 #sound-dai-cells = <0>;
387 reg = <0xa0000 0x2210>;