Lines Matching +full:0 +full:x82000000
22 #size-cells = <0>;
24 cpu0: cpu@0 {
28 reg = <0>;
34 marvell,tauros2-cache-features = <0>;
46 #size-cells = <0>;
51 pinctrl-0 = <&pmx_i2cmux_0>;
55 i2c0: i2c@0 {
56 reg = <0>;
58 #size-cells = <0>;
65 #size-cells = <0>;
73 #size-cells = <0>;
84 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
85 pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
87 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
88 MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
89 MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
90 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
91 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
101 bus-range = <0x00 0xff>;
103 ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
104 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
105 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
106 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
107 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
108 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
113 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
114 reg = <0x0800 0 0 0 0>;
116 marvell,pcie-port = <0>;
120 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
121 0x81000000 0 0 0x81000000 0x1 0 1 0>;
122 bus-range = <0x00 0xff>;
127 interrupt-map-mask = <0 0 0 7>;
128 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
129 <0 0 0 2 &pcie0_intc 1>,
130 <0 0 0 3 &pcie0_intc 2>,
131 <0 0 0 4 &pcie0_intc 3>;
142 assigned-addresses = <0x82001000 0 0x80000 0 0x2000>;
143 reg = <0x1000 0 0 0 0>;
149 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
150 0x81000000 0 0 0x81000000 0x2 0 1 0>;
151 bus-range = <0x00 0xff>;
156 interrupt-map-mask = <0 0 0 7>;
157 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
158 <0 0 0 2 &pcie1_intc 1>,
159 <0 0 0 3 &pcie1_intc 2>,
160 <0 0 0 4 &pcie1_intc 3>;
173 ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
174 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
175 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
176 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
181 #size-cells = <0>;
182 cell-index = <0>;
184 reg = <0x10600 0x28>;
185 clocks = <&core_clk 0>;
186 pinctrl-0 = <&pmx_spi0>;
193 reg = <0x11000 0x20>;
195 #size-cells = <0>;
198 clocks = <&core_clk 0>;
204 reg = <0x12000 0x100>;
207 clocks = <&core_clk 0>;
213 reg = <0x12100 0x100>;
216 clocks = <&core_clk 0>;
217 pinctrl-0 = <&pmx_uart1>;
224 reg = <0x12200 0x100>;
227 clocks = <&core_clk 0>;
233 reg = <0x12300 0x100>;
236 clocks = <&core_clk 0>;
243 #size-cells = <0>;
246 reg = <0x14600 0x28>;
247 clocks = <&core_clk 0>;
253 reg = <0x20000 0x80>, <0x800100 0x8>;
258 reg = <0x20000 0x110>;
265 reg = <0x20110 0x8>;
266 interrupts = <0>;
274 reg = <0x20200 0x10>, <0x20210 0x10>;
279 reg = <0x20300 0x20>;
282 clocks = <&core_clk 0>;
287 reg = <0x20300 0x28>, <0x20108 0x4>;
290 clocks = <&core_clk 0>;
295 reg = <0x30000 0x10000>;
300 marvell,crypto-sram-size = <0x800>;
306 reg = <0x50000 0x1000>;
308 clocks = <&gate_clk 0>;
314 reg = <0x51000 0x1000>;
322 reg = <0x60800 0x100
323 0x60a00 0x100>;
342 reg = <0x60900 0x100
343 0x60b00 0x100>;
362 reg = <0x90000 0x100>;
365 pinctrl-0 = <&pmx_sdio1>;
373 #size-cells = <0>;
374 reg = <0x72000 0x4000>;
379 ethernet-port@0 {
381 reg = <0>;
391 #size-cells = <0>;
392 reg = <0x72004 0x84>;
400 reg = <0x92000 0x100>;
403 pinctrl-0 = <&pmx_sdio0>;
410 reg = <0xa0000 0x2400>;
421 reg = <0xa2000 0x0334>;
424 #phy-cells = <0>;
430 reg = <0xb0000 0x2210>;
439 reg = <0xb4000 0x2210>;
448 reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
449 ranges = <0x00000000 0x000d0000 0x8000
450 0x00008000 0x000d8000 0x8000>;
460 #power-domain-cells = <0>;
461 marvell,pmu_pwr_mask = <0x00000008>;
462 marvell,pmu_iso_mask = <0x00000001>;
467 #power-domain-cells = <0>;
468 marvell,pmu_pwr_mask = <0x00000004>;
469 marvell,pmu_iso_mask = <0x00000002>;
476 reg = <0x001c 0x0c>, <0x005c 0x08>;
481 reg = <0x0038 0x4>;
482 clocks = <&core_clk 0>;
488 reg = <0x0064 0x8>;
494 reg = <0x0200 0x14>,
495 <0x0440 0x04>;
498 pmx_gpio_0: pmx-gpio-0 {
720 pmx_i2cmux_0: pmx-i2cmux-0 {
738 reg = <0x0214 0x4>;
746 reg = <0x0400 0x20>;
758 reg = <0x0420 0x20>;
768 reg = <0x8500 0x20>;
776 reg = <0xe802c 0x14>;
783 reg = <0xe8400 0x0c>;
789 reg = <0x810000 0x1000>;
796 reg = <0x820000 0x1000>;
803 reg = <0xffffe000 0x800>;
815 reg = <0x840000 0x4000>;