Lines Matching +full:0 +full:x500
35 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
41 reg = <0x1400 0x500>;
46 reg = <0x08000 0x1000>;
47 cache-id-part = <0x100>;
55 pinctrl-0 = <&uart2_pins>;
57 reg = <0x12200 0x100>;
61 clocks = <&coreclk 0>;
67 pinctrl-0 = <&uart3_pins>;
69 reg = <0x12300 0x100>;
73 clocks = <&coreclk 0>;
79 reg = <0x18200 0x500>;
84 reg = <0x18220 0x4>;
85 clocks = <&coreclk 0>;
91 reg = <0x18230 0x08>;
97 reg = <0x182b0 0x4
98 0x184d0 0x4>;
105 reg = <0x18700 0x24>, <0x1c054 0x10>;
111 reg = <0x21000 0x8>;
116 reg = <0x30000 0x4000>;
124 reg = <0x52000 0x500>;
132 reg = <0x60900 0x100
133 0x60b00 0x100>;
160 reg = <0x90000 0x10000>;
167 marvell,crypto-sram-size = <0x800>;
172 reg = <0xc0000 0xac>;
180 reg = <0xF0900 0x100
181 0xF0B00 0x100>;
201 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
205 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
210 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
214 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
219 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
220 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
233 #clock-cells = <0>;
241 reg = <0x11000 0x100>;
246 reg = <0x11100 0x100>;
250 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
267 reg = <0x20800 0x20>;
337 pinctrl-0 = <&spi0_pins>;
343 pinctrl-0 = <&spi1_pins>;