Lines Matching +full:3 +full:- +full:port
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
44 clock-latency = <1000000>;
49 compatible = "marvell,sheeva-v7";
52 clock-latency = <1000000>;
55 cpu@3 {
57 compatible = "marvell,sheeva-v7";
58 reg = <3>;
59 clocks = <&cpuclk 3>;
60 clock-latency = <1000000>;
71 compatible = "marvell,armada-xp-pcie";
75 #address-cells = <3>;
76 #size-cells = <2>;
78 msi-parent = <&mpic>;
79 bus-range = <0x00 0xff>;
82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
86 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
87 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
88 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
89 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
90 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
91 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
92 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
93 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
94 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
95 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
96 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
97 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
98 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
99 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
101 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
102 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
103 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
104 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
105 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
106 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
107 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
108 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
110 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
111 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
113 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
114 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
118 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
120 #address-cells = <3>;
121 #size-cells = <2>;
122 interrupt-names = "intx";
123 interrupts-extended = <&mpic 58>;
124 #interrupt-cells = <1>;
127 bus-range = <0x00 0xff>;
128 interrupt-map-mask = <0 0 0 7>;
129 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
131 <0 0 0 3 &pcie1_intc 2>,
132 <0 0 0 4 &pcie1_intc 3>;
133 marvell,pcie-port = <0>;
134 marvell,pcie-lane = <0>;
138 pcie1_intc: interrupt-controller {
139 interrupt-controller;
140 #interrupt-cells = <1>;
146 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
148 #address-cells = <3>;
149 #size-cells = <2>;
150 interrupt-names = "intx";
151 interrupts-extended = <&mpic 59>;
152 #interrupt-cells = <1>;
155 bus-range = <0x00 0xff>;
156 interrupt-map-mask = <0 0 0 7>;
157 interrupt-map = <0 0 0 1 &pcie2_intc 0>,
159 <0 0 0 3 &pcie2_intc 2>,
160 <0 0 0 4 &pcie2_intc 3>;
161 marvell,pcie-port = <0>;
162 marvell,pcie-lane = <1>;
166 pcie2_intc: interrupt-controller {
167 interrupt-controller;
168 #interrupt-cells = <1>;
172 pcie3: pcie@3,0 {
174 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
176 #address-cells = <3>;
177 #size-cells = <2>;
178 interrupt-names = "intx";
179 interrupts-extended = <&mpic 60>;
180 #interrupt-cells = <1>;
183 bus-range = <0x00 0xff>;
184 interrupt-map-mask = <0 0 0 7>;
185 interrupt-map = <0 0 0 1 &pcie3_intc 0>,
187 <0 0 0 3 &pcie3_intc 2>,
188 <0 0 0 4 &pcie3_intc 3>;
189 marvell,pcie-port = <0>;
190 marvell,pcie-lane = <2>;
194 pcie3_intc: interrupt-controller {
195 interrupt-controller;
196 #interrupt-cells = <1>;
202 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
204 #address-cells = <3>;
205 #size-cells = <2>;
206 interrupt-names = "intx";
207 interrupts-extended = <&mpic 61>;
208 #interrupt-cells = <1>;
211 bus-range = <0x00 0xff>;
212 interrupt-map-mask = <0 0 0 7>;
213 interrupt-map = <0 0 0 1 &pcie4_intc 0>,
215 <0 0 0 3 &pcie4_intc 2>,
216 <0 0 0 4 &pcie4_intc 3>;
217 marvell,pcie-port = <0>;
218 marvell,pcie-lane = <3>;
222 pcie4_intc: interrupt-controller {
223 interrupt-controller;
224 #interrupt-cells = <1>;
230 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
232 #address-cells = <3>;
233 #size-cells = <2>;
234 interrupt-names = "intx";
235 interrupts-extended = <&mpic 62>;
236 #interrupt-cells = <1>;
239 bus-range = <0x00 0xff>;
240 interrupt-map-mask = <0 0 0 7>;
241 interrupt-map = <0 0 0 1 &pcie5_intc 0>,
243 <0 0 0 3 &pcie5_intc 2>,
244 <0 0 0 4 &pcie5_intc 3>;
245 marvell,pcie-port = <1>;
246 marvell,pcie-lane = <0>;
250 pcie5_intc: interrupt-controller {
251 interrupt-controller;
252 #interrupt-cells = <1>;
258 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
260 #address-cells = <3>;
261 #size-cells = <2>;
262 interrupt-names = "intx";
263 interrupts-extended = <&mpic 63>;
264 #interrupt-cells = <1>;
267 bus-range = <0x00 0xff>;
268 interrupt-map-mask = <0 0 0 7>;
269 interrupt-map = <0 0 0 1 &pcie6_intc 0>,
271 <0 0 0 3 &pcie6_intc 2>,
272 <0 0 0 4 &pcie6_intc 3>;
273 marvell,pcie-port = <1>;
274 marvell,pcie-lane = <1>;
278 pcie6_intc: interrupt-controller {
279 interrupt-controller;
280 #interrupt-cells = <1>;
286 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
288 #address-cells = <3>;
289 #size-cells = <2>;
290 interrupt-names = "intx";
291 interrupts-extended = <&mpic 64>;
292 #interrupt-cells = <1>;
295 bus-range = <0x00 0xff>;
296 interrupt-map-mask = <0 0 0 7>;
297 interrupt-map = <0 0 0 1 &pcie7_intc 0>,
299 <0 0 0 3 &pcie7_intc 2>,
300 <0 0 0 4 &pcie7_intc 3>;
301 marvell,pcie-port = <1>;
302 marvell,pcie-lane = <2>;
306 pcie7_intc: interrupt-controller {
307 interrupt-controller;
308 #interrupt-cells = <1>;
314 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
316 #address-cells = <3>;
317 #size-cells = <2>;
318 interrupt-names = "intx";
319 interrupts-extended = <&mpic 65>;
320 #interrupt-cells = <1>;
323 bus-range = <0x00 0xff>;
324 interrupt-map-mask = <0 0 0 7>;
325 interrupt-map = <0 0 0 1 &pcie8_intc 0>,
327 <0 0 0 3 &pcie8_intc 2>,
328 <0 0 0 4 &pcie8_intc 3>;
329 marvell,pcie-port = <1>;
330 marvell,pcie-lane = <3>;
334 pcie8_intc: interrupt-controller {
335 interrupt-controller;
336 #interrupt-cells = <1>;
342 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
344 #address-cells = <3>;
345 #size-cells = <2>;
346 interrupt-names = "intx";
347 interrupts-extended = <&mpic 99>;
348 #interrupt-cells = <1>;
351 bus-range = <0x00 0xff>;
352 interrupt-map-mask = <0 0 0 7>;
353 interrupt-map = <0 0 0 1 &pcie9_intc 0>,
355 <0 0 0 3 &pcie9_intc 2>,
356 <0 0 0 4 &pcie9_intc 3>;
357 marvell,pcie-port = <2>;
358 marvell,pcie-lane = <0>;
362 pcie9_intc: interrupt-controller {
363 interrupt-controller;
364 #interrupt-cells = <1>;
370 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
372 #address-cells = <3>;
373 #size-cells = <2>;
374 interrupt-names = "intx";
375 interrupts-extended = <&mpic 103>;
376 #interrupt-cells = <1>;
379 bus-range = <0x00 0xff>;
380 interrupt-map-mask = <0 0 0 7>;
381 interrupt-map = <0 0 0 1 &pcie10_intc 0>,
383 <0 0 0 3 &pcie10_intc 2>,
384 <0 0 0 4 &pcie10_intc 3>;
385 marvell,pcie-port = <3>;
386 marvell,pcie-lane = <0>;
390 pcie10_intc: interrupt-controller {
391 interrupt-controller;
392 #interrupt-cells = <1>;
397 internal-regs {
399 compatible = "marvell,armada-370-gpio",
400 "marvell,orion-gpio";
402 reg-names = "gpio", "pwm";
404 gpio-controller;
405 #gpio-cells = <2>;
406 #pwm-cells = <2>;
407 interrupt-controller;
408 #interrupt-cells = <2>;
414 compatible = "marvell,armada-370-gpio",
415 "marvell,orion-gpio";
417 reg-names = "gpio", "pwm";
419 gpio-controller;
420 #gpio-cells = <2>;
421 #pwm-cells = <2>;
422 interrupt-controller;
423 #interrupt-cells = <2>;
429 compatible = "marvell,armada-370-gpio",
430 "marvell,orion-gpio";
432 ngpios = <3>;
433 gpio-controller;
434 #gpio-cells = <2>;
435 interrupt-controller;
436 #interrupt-cells = <2>;
441 compatible = "marvell,armada-xp-neta";
452 compatible = "marvell,mv78460-pinctrl";