Lines Matching +full:0 +full:x81000000
26 #size-cells = <0>;
29 cpu@0 {
32 reg = <0>;
33 clocks = <&cpuclk 0>;
48 * MV78230 has 2 PCIe units Gen2.0: One unit can be
61 bus-range = <0x00 0xff>;
64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
68 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
69 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
70 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
71 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
72 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
73 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
74 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
75 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
76 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
77 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
78 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
80 pcie1: pcie@1,0 {
82 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
83 reg = <0x0800 0 0 0 0>;
89 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
90 0x81000000 0 0 0x81000000 0x1 0 1 0>;
91 bus-range = <0x00 0xff>;
92 interrupt-map-mask = <0 0 0 7>;
93 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
94 <0 0 0 2 &pcie1_intc 1>,
95 <0 0 0 3 &pcie1_intc 2>,
96 <0 0 0 4 &pcie1_intc 3>;
97 marvell,pcie-port = <0>;
98 marvell,pcie-lane = <0>;
108 pcie2: pcie@2,0 {
110 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
111 reg = <0x1000 0 0 0 0>;
117 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
118 0x81000000 0 0 0x81000000 0x2 0 1 0>;
119 bus-range = <0x00 0xff>;
120 interrupt-map-mask = <0 0 0 7>;
121 interrupt-map = <0 0 0 1 &pcie2_intc 0>,
122 <0 0 0 2 &pcie2_intc 1>,
123 <0 0 0 3 &pcie2_intc 2>,
124 <0 0 0 4 &pcie2_intc 3>;
125 marvell,pcie-port = <0>;
136 pcie3: pcie@3,0 {
138 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
139 reg = <0x1800 0 0 0 0>;
145 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
146 0x81000000 0 0 0x81000000 0x3 0 1 0>;
147 bus-range = <0x00 0xff>;
148 interrupt-map-mask = <0 0 0 7>;
149 interrupt-map = <0 0 0 1 &pcie3_intc 0>,
150 <0 0 0 2 &pcie3_intc 1>,
151 <0 0 0 3 &pcie3_intc 2>,
152 <0 0 0 4 &pcie3_intc 3>;
153 marvell,pcie-port = <0>;
164 pcie4: pcie@4,0 {
166 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
167 reg = <0x2000 0 0 0 0>;
173 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
174 0x81000000 0 0 0x81000000 0x4 0 1 0>;
175 bus-range = <0x00 0xff>;
176 interrupt-map-mask = <0 0 0 7>;
177 interrupt-map = <0 0 0 1 &pcie4_intc 0>,
178 <0 0 0 2 &pcie4_intc 1>,
179 <0 0 0 3 &pcie4_intc 2>,
180 <0 0 0 4 &pcie4_intc 3>;
181 marvell,pcie-port = <0>;
192 pcie5: pcie@5,0 {
194 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
195 reg = <0x2800 0 0 0 0>;
201 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
202 0x81000000 0 0 0x81000000 0x5 0 1 0>;
203 bus-range = <0x00 0xff>;
204 interrupt-map-mask = <0 0 0 7>;
205 interrupt-map = <0 0 0 1 &pcie5_intc 0>,
206 <0 0 0 2 &pcie5_intc 1>,
207 <0 0 0 3 &pcie5_intc 2>,
208 <0 0 0 4 &pcie5_intc 3>;
210 marvell,pcie-lane = <0>;
225 reg = <0x18100 0x40>, <0x181c0 0x08>;
234 clocks = <&coreclk 0>;
240 reg = <0x18140 0x40>, <0x181c8 0x08>;
249 clocks = <&coreclk 0>;