Lines Matching +full:0 +full:xf0000000

13  * internal registers to 0xf1000000 (instead of the default
14  * 0xd0000000). The 0xf1000000 is the default used by the recent,
17  * left internal registers mapped at 0xd0000000. If you are in this
34 	memory@0 {
41                  * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
45 		reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
46 		      <0x00000001 0x00000000 0x00000001 0x00000000>;
58 		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
59 			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
60 			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
61 			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
62 			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
63 			  MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
73 			devbus,badr-skew-ps = <0>;
76 			devbus,rd-setup-ps  = <0>;
77 			devbus,rd-hold-ps   = <0>;
80 			devbus,sync-enable = <0>;
86 			nor@0 {
88 				reg = <0 0x1000000>;
107 				pinctrl-0 = <&pic_pins>;
109 				pic_pins: pic-pins-0 {
125 				bm,pool-long = <0>;
166 				nand@0 {
167 					reg = <0>;
168 					label = "pxa3xx_nand-0";
169 					nand-rb = <0>;
188 	pcie@1,0 {
189 		/* Port 0, Lane 0 */
192 	pcie@9,0 {
193 		/* Port 2, Lane 0 */
196 	pcie@a,0 {
197 		/* Port 3, Lane 0 */
203 	phy0: ethernet-phy@0 {
223 	flash@0 {
227 		reg = <0>; /* Chip select 0 */