dts/marvell/armada-39x.dtsi

32 		#size-cells = <0>;
35 		cpu@0 {
38 			reg = <0>;
59 		pcie-mem-aperture = <0xe0000000 0x8000000>;
60 		pcie-io-aperture  = <0xe8000000 0x100000>;
64 			reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
71 			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
75 				reg = <0x8000 0x1000>;
78 				arm,double-linefill-incr = <0>;
79 				arm,double-linefill-wrap = <0>;
80 				arm,double-linefill = <0>;
86 				reg = <0xc000 0x100>;
91 				reg = <0xc600 0x20>;
99 				#size-cells = <0>;
101 				reg = <0xd000 0x1000>,
102 				      <0xc100 0x100>;
107 				reg = <0x11000 0x20>;
109 				#size-cells = <0>;
111 				clocks = <&coreclk 0>;
117 				reg = <0x11100 0x20>;
119 				#size-cells = <0>;
121 				clocks = <&coreclk 0>;
127 				reg = <0x11200 0x20>;
129 				#size-cells = <0>;
131 				clocks = <&coreclk 0>;
137 				reg = <0x11300 0x20>;
139 				#size-cells = <0>;
141 				clocks = <&coreclk 0>;
147 				reg = <0x12000 0x100>;
151 				clocks = <&coreclk 0>;
157 				reg = <0x12100 0x100>;
161 				clocks = <&coreclk 0>;
167 				reg = <0x12200 0x100>;
171 				clocks = <&coreclk 0>;
177 				reg = <0x12300 0x100>;
181 				clocks = <&coreclk 0>;
217 				reg = <0x18100 0x40>;
231 				reg = <0x18140 0x40>;
246 				reg = <0x18200 0x100>;
251 				reg = <0x18220 0x4>;
252 				clocks = <&coreclk 0>;
258 				reg = <0x18600 0x04>;
264 				reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
269 				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
279 				reg = <0x20300 0x30>, <0x21040 0x30>;
292 				reg = <0x20300 0x34>, <0x20704 0x4>,
293 				      <0x18260 0x4>;
300 				reg = <0x20800 0x10>;
305 				reg = <0x20d20 0x6c>;
310 				reg = <0x21010 0x1c>;
316 				reg = <0x22000 0x1000>;
321 				reg = <0x60800 0x100
322 				       0x60a00 0x100>;
341 				reg = <0x60900 0x100
342 				       0x60b00 0x100>;
361 				reg = <0xa3800 0x20>, <0x184a0 0x0c>;
368 				reg = <0xd0000 0x54>;
370 				#size-cells = <0>;
372 				clocks = <&coredivclk 0>;
379 				reg = <0xd8000 0x1000>,
380 					<0xdc000 0x100>,
381 					<0x18454 0x4>;
384 				mrvl,clk-delay-cycles = <0x1F>;
391 				reg = <0xe4250 0xc>;
399 				reg = <0xe4078 0x4>, <0xe4074 0x4>;
413 			bus-range = <0x00 0xff>;
416 			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
417 				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
418 				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
419 				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
420 				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
421 				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
422 				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
423 				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
424 				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
425 				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
426 				0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
427 				0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;
432 			 * pcie@4,0 is not available.
434 			pcie@1,0 {
436 				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
437 				reg = <0x0800 0 0 0 0>;
443 				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
444 					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
445 				bus-range = <0x00 0xff>;
446 				interrupt-map-mask = <0 0 0 7>;
447 				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
448 						<0 0 0 2 &pcie1_intc 1>,
449 						<0 0 0 3 &pcie1_intc 2>,
450 						<0 0 0 4 &pcie1_intc 3>;
451 				marvell,pcie-port = <0>;
452 				marvell,pcie-lane = <0>;
463 			pcie@2,0 {
465 				assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
466 				reg = <0x1000 0 0 0 0>;
472 				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
473 					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
474 				bus-range = <0x00 0xff>;
475 				interrupt-map-mask = <0 0 0 7>;
476 				interrupt-map = <0 0 0 1 &pcie2_intc 0>,
477 						<0 0 0 2 &pcie2_intc 1>,
478 						<0 0 0 3 &pcie2_intc 2>,
479 						<0 0 0 4 &pcie2_intc 3>;
481 				marvell,pcie-lane = <0>;
492 			pcie@3,0 {
494 				assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
495 				reg = <0x1800 0 0 0 0>;
501 				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
502 					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
503 				bus-range = <0x00 0xff>;
504 				interrupt-map-mask = <0 0 0 7>;
505 				interrupt-map = <0 0 0 1 &pcie3_intc 0>,
506 						<0 0 0 2 &pcie3_intc 1>,
507 						<0 0 0 3 &pcie3_intc 2>,
508 						<0 0 0 4 &pcie3_intc 3>;
510 				marvell,pcie-lane = <0>;
521 			 * x1 port only available when pcie@1,0 is
524 			pcie@4,0 {
526 				assigned-addresses = <0x82002000 0 0x48000 0 0x2000>;
527 				reg = <0x2000 0 0 0 0>;
533 				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
534 					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
535 				bus-range = <0x00 0xff>;
536 				interrupt-map-mask = <0 0 0 7>;
537 				interrupt-map = <0 0 0 1 &pcie4_intc 0>,
538 						<0 0 0 2 &pcie4_intc 1>,
539 						<0 0 0 3 &pcie4_intc 2>,
540 						<0 0 0 4 &pcie4_intc 3>;
542 				marvell,pcie-lane = <0>;
556 			reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
558 			#size-cells = <0>;
559 			cell-index = <0>;
561 			clocks = <&coreclk 0>;
568 			reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
570 			#size-cells = <0>;
573 			clocks = <&coreclk 0>;
582 			#clock-cells = <0>;
589 			#clock-cells = <0>;