dts/marvell/armada-385.dtsi

20 		#size-cells = <0>;
23 		cpu@0 {
26 			reg = <0>;
45 			bus-range = <0x00 0xff>;
48 			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
49 				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
50 				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
51 				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
52 				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
53 				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
54 				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
55 				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
56 				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
57 				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
58 				0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
59 				0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;
64 			 * pcie@4,0 is not available.
66 			pcie1: pcie@1,0 {
68 				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
69 				reg = <0x0800 0 0 0 0>;
75 				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
76 					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
77 				bus-range = <0x00 0xff>;
78 				interrupt-map-mask = <0 0 0 7>;
79 				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
80 						<0 0 0 2 &pcie1_intc 1>,
81 						<0 0 0 3 &pcie1_intc 2>,
82 						<0 0 0 4 &pcie1_intc 3>;
83 				marvell,pcie-port = <0>;
84 				marvell,pcie-lane = <0>;
94 			pcie2: pcie@2,0 {
96 				assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
97 				reg = <0x1000 0 0 0 0>;
103 				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
104 					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
105 				bus-range = <0x00 0xff>;
106 				interrupt-map-mask = <0 0 0 7>;
107 				interrupt-map = <0 0 0 1 &pcie2_intc 0>,
108 						<0 0 0 2 &pcie2_intc 1>,
109 						<0 0 0 3 &pcie2_intc 2>,
110 						<0 0 0 4 &pcie2_intc 3>;
112 				marvell,pcie-lane = <0>;
122 			pcie3: pcie@3,0 {
124 				assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
125 				reg = <0x1800 0 0 0 0>;
131 				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
132 					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
133 				bus-range = <0x00 0xff>;
134 				interrupt-map-mask = <0 0 0 7>;
135 				interrupt-map = <0 0 0 1 &pcie3_intc 0>,
136 						<0 0 0 2 &pcie3_intc 1>,
137 						<0 0 0 3 &pcie3_intc 2>,
138 						<0 0 0 4 &pcie3_intc 3>;
140 				marvell,pcie-lane = <0>;
150 			 * x1 port only available when pcie@1,0 is
153 			pcie4: pcie@4,0 {
155 				assigned-addresses = <0x82002000 0 0x48000 0 0x2000>;
156 				reg = <0x2000 0 0 0 0>;
162 				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
163 					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
164 				bus-range = <0x00 0xff>;
165 				interrupt-map-mask = <0 0 0 7>;
166 				interrupt-map = <0 0 0 1 &pcie4_intc 0>,
167 						<0 0 0 2 &pcie4_intc 1>,
168 						<0 0 0 3 &pcie4_intc 2>,
169 						<0 0 0 4 &pcie4_intc 3>;
171 				marvell,pcie-lane = <0>;