dts/marvell/armada-370.dtsi

35 			reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
47 			bus-range = <0x00 0xff>;
50 			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
51 				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
52 				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
53 				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
54 				0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */
55 				0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;
57 			pcie0: pcie@1,0 {
59 				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
60 				reg = <0x0800 0 0 0 0>;
66                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
67                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
68 				bus-range = <0x00 0xff>;
69 				interrupt-map-mask = <0 0 0 7>;
70 				interrupt-map = <0 0 0 1 &pcie0_intc 0>,
71 						<0 0 0 2 &pcie0_intc 1>,
72 						<0 0 0 3 &pcie0_intc 2>,
73 						<0 0 0 4 &pcie0_intc 3>;
74 				marvell,pcie-port = <0>;
75 				marvell,pcie-lane = <0>;
85 			pcie2: pcie@2,0 {
87 				assigned-addresses = <0x82001000 0 0x80000 0 0x2000>;
88 				reg = <0x1000 0 0 0 0>;
94                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
95                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
96 				bus-range = <0x00 0xff>;
97 				interrupt-map-mask = <0 0 0 7>;
98 				interrupt-map = <0 0 0 1 &pcie2_intc 0>,
99 						<0 0 0 2 &pcie2_intc 1>,
100 						<0 0 0 3 &pcie2_intc 2>,
101 						<0 0 0 4 &pcie2_intc 3>;
103 				marvell,pcie-lane = <0>;
117 				reg = <0x08000 0x1000>;
118 				cache-id-part = <0x100>;
127 				reg = <0x18100 0x40>, <0x181c0 0x08>;
136 				clocks = <&coreclk 0>;
142 				reg = <0x18140 0x40>, <0x181c8 0x08>;
151 				clocks = <&coreclk 0>;
157 				reg = <0x18180 0x40>;
169 				reg = <0x18200 0x100>;
174 				reg = <0x18220 0x4>;
175 				clocks = <&coreclk 0>;
181 				reg = <0x18230 0x08>;
187 				reg = <0x18300 0x4
188 					0x18304 0x4>;
193 				reg = <0x18330 0x4>;
198 				reg = <0x21000 0x8>;
204 				reg = <0x30000 0x4000>;
206 				clocks = <&gateclk 0>;
213 				reg = <0x60800 0x100
214 				       0x60A00 0x100>;
232 				reg = <0x60900 0x100
233 				       0x60b00 0x100>;
251 				reg = <0x90000 0x10000>;
257 				marvell,crypto-sram-size = <0x7e0>;
263 			reg = <MBUS_ID(0x09, 0x01) 0 0x800>;
268 			ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>;
277 			idle-sram@0 {
278 				reg = <0x0 0x20>;
290 	pinctrl-0 = <&uart0_pins>;
295 	pinctrl-0 = <&uart1_pins>;
300 	reg = <0x11000 0x20>;
304 	reg = <0x11100 0x20>;
308 	reg = <0x20a00 0x1d0>, <0x21870 0x58>;
322 	clocks = <&coreclk 0>;
326 	clocks = <&coreclk 0>;
431 	pinctrl-0 = <&spi0_pins1>;
437 	pinctrl-0 = <&spi1_pins>;