Lines Matching +full:0 +full:x800000
11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * left internal registers mapped at 0xd0000000. If you are in this
35 memory@0 {
37 reg = <0x00000000 0x20000000>; /* 512 MB */
41 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
42 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
43 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
60 pinctrl-0 = <&ge1_rgmii_pins>;
71 pinctrl-0 = <&sdio_pins1>;
98 gpio-fan,speed-map = <0 0>, <3000 1>;
99 pinctrl-0 = <&fan_pins>;
106 pinctrl-0 = <&led_pins>;
110 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
122 pcie@1,0 {
123 /* Port 0, Lane 0 */
128 pcie@2,0 {
129 /* Port 1, Lane 0 */
135 pinctrl-0 = <&mdio_pins>;
137 phy0: ethernet-phy@0 {
138 reg = <0>;
141 #size-cells = <0>;
143 led@0 {
144 reg = <0>;
154 reg = <0x10>;
160 #size-cells = <0>;
162 ethernet-port@0 {
163 reg = <0>;
195 #size-cells = <0>;
197 switchphy0: ethernet-phy@0 {
198 reg = <0>;
200 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
240 nand@0 {
241 reg = <0>;
242 label = "pxa3xx_nand-0";
243 nand-rb = <0>;
252 partition@0 {
254 reg = <0 0x800000>;
258 reg = <0x800000 0x800000>;
262 reg = <0x1000000 0x3f000000>;