Lines Matching +full:pmu +full:- +full:gate
1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
25 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
32 pmu: pmu@ff111000 { label
33 compatible = "arm,cortex-a9-pmu";
34 interrupt-parent = <&intc>;
36 interrupt-affinity = <&cpu0>, <&cpu1>;
41 intc: interrupt-controller@ffffd000 {
42 compatible = "arm,cortex-a9-gic";
43 #interrupt-cells = <3>;
44 interrupt-controller;
50 #address-cells = <1>;
51 #size-cells = <1>;
52 compatible = "simple-bus";
54 interrupt-parent = <&intc>;
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
75 #dma-cells = <1>;
77 clock-names = "apb_pclk";
79 reset-names = "dma", "dma-ocp";
84 #address-cells = <0x1>;
85 #size-cells = <0x1>;
87 compatible = "fpga-region";
88 fpga-mgr = <&fpga_mgr>;
92 compatible = "altr,clk-mgr";
96 #address-cells = <1>;
97 #size-cells = <0>;
100 #clock-cells = <0>;
101 compatible = "fixed-clock";
105 #clock-cells = <0>;
106 compatible = "fixed-clock";
110 #clock-cells = <0>;
111 compatible = "fixed-clock";
115 #clock-cells = <0>;
116 compatible = "fixed-clock";
120 #address-cells = <1>;
121 #size-cells = <0>;
122 #clock-cells = <0>;
123 compatible = "altr,socfpga-a10-pll-clock";
129 #clock-cells = <0>;
130 compatible = "altr,socfpga-a10-perip-clk";
132 div-reg = <0x140 0 11>;
136 #clock-cells = <0>;
137 compatible = "altr,socfpga-a10-perip-clk";
139 div-reg = <0x144 0 11>;
143 #clock-cells = <0>;
144 compatible = "altr,socfpga-a10-perip-clk";
150 #clock-cells = <0>;
151 compatible = "altr,socfpga-a10-perip-clk";
157 #clock-cells = <0>;
158 compatible = "altr,socfpga-a10-perip-clk";
164 #clock-cells = <0>;
165 compatible = "altr,socfpga-a10-perip-clk";
171 #clock-cells = <0>;
172 compatible = "altr,socfpga-a10-perip-clk"
179 #clock-cells = <0>;
180 compatible = "altr,socfpga-a10-perip-clk";
186 #clock-cells = <0>;
187 compatible = "altr,socfpga-a10-perip-clk";
193 #clock-cells = <0>;
194 compatible = "altr,socfpga-a10-perip-clk";
200 #clock-cells = <0>;
201 compatible = "altr,socfpga-a10-perip-clk";
208 #address-cells = <1>;
209 #size-cells = <0>;
210 #clock-cells = <0>;
211 compatible = "altr,socfpga-a10-pll-clock";
217 #clock-cells = <0>;
218 compatible = "altr,socfpga-a10-perip-clk";
220 div-reg = <0x140 16 11>;
224 #clock-cells = <0>;
225 compatible = "altr,socfpga-a10-perip-clk";
227 div-reg = <0x144 16 11>;
231 #clock-cells = <0>;
232 compatible = "altr,socfpga-a10-perip-clk";
238 #clock-cells = <0>;
239 compatible = "altr,socfpga-a10-perip-clk";
245 #clock-cells = <0>;
246 compatible = "altr,socfpga-a10-perip-clk";
252 #clock-cells = <0>;
253 compatible = "altr,socfpga-a10-perip-clk";
259 #clock-cells = <0>;
260 compatible = "altr,socfpga-a10-perip-clk";
266 #clock-cells = <0>;
267 compatible = "altr,socfpga-a10-perip-clk";
273 #clock-cells = <0>;
274 compatible = "altr,socfpga-a10-perip-clk";
280 #clock-cells = <0>;
281 compatible = "altr,socfpga-a10-perip-clk";
288 #clock-cells = <0>;
289 compatible = "altr,socfpga-a10-perip-clk";
297 #clock-cells = <0>;
298 compatible = "altr,socfpga-a10-perip-clk";
306 #clock-cells = <0>;
307 compatible = "altr,socfpga-a10-perip-clk";
315 #clock-cells = <0>;
316 compatible = "altr,socfpga-a10-perip-clk";
320 fixed-divider = <4>;
325 #clock-cells = <0>;
326 compatible = "altr,socfpga-a10-perip-clk";
328 fixed-divider = <4>;
332 #clock-cells = <0>;
333 compatible = "altr,socfpga-a10-gate-clk";
335 div-reg = <0xA8 0 2>;
336 clk-gate = <0x48 1>;
340 #clock-cells = <0>;
341 compatible = "altr,socfpga-a10-gate-clk";
343 div-reg = <0xA8 8 2>;
344 clk-gate = <0x48 2>;
348 #clock-cells = <0>;
349 compatible = "altr,socfpga-a10-gate-clk";
351 div-reg = <0xA8 16 2>;
352 clk-gate = <0x48 3>;
356 #clock-cells = <0>;
357 compatible = "altr,socfpga-a10-gate-clk";
359 fixed-divider = <4>;
360 clk-gate = <0x48 0>;
364 #clock-cells = <0>;
365 compatible = "altr,socfpga-a10-gate-clk";
367 clk-gate = <0xC8 5>;
371 #clock-cells = <0>;
372 compatible = "altr,socfpga-a10-gate-clk";
374 clk-gate = <0xC8 11>;
378 #clock-cells = <0>;
379 compatible = "altr,socfpga-a10-gate-clk";
381 clk-gate = <0xC8 10>;
385 #clock-cells = <0>;
386 compatible = "altr,socfpga-a10-gate-clk";
388 clk-gate = <0xC8 10>;
392 #clock-cells = <0>;
393 compatible = "altr,socfpga-a10-gate-clk";
395 fixed-divider = <4>;
396 clk-gate = <0xC8 10>;
400 #clock-cells = <0>;
401 compatible = "altr,socfpga-a10-gate-clk";
403 clk-gate = <0xC8 9>;
407 #clock-cells = <0>;
408 compatible = "altr,socfpga-a10-gate-clk";
410 clk-gate = <0xC8 8>;
414 #clock-cells = <0>;
415 compatible = "altr,socfpga-a10-gate-clk";
417 clk-gate = <0xC8 6>;
422 socfpga_axi_setup: stmmac-axi-config {
429 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
430 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
433 interrupt-names = "macirq";
435 mac-address = [00 00 00 00 00 00];
436 snps,multicast-filter-bins = <256>;
437 snps,perfect-filter-entries = <128>;
438 tx-fifo-depth = <4096>;
439 rx-fifo-depth = <16384>;
441 clock-names = "stmmaceth", "ptp_ref";
443 reset-names = "stmmaceth", "ahb";
444 snps,axi-config = <&socfpga_axi_setup>;
449 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
450 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
453 interrupt-names = "macirq";
455 mac-address = [00 00 00 00 00 00];
456 snps,multicast-filter-bins = <256>;
457 snps,perfect-filter-entries = <128>;
458 tx-fifo-depth = <4096>;
459 rx-fifo-depth = <16384>;
461 clock-names = "stmmaceth", "ptp_ref";
463 reset-names = "stmmaceth", "ahb";
464 snps,axi-config = <&socfpga_axi_setup>;
469 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
470 altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
473 interrupt-names = "macirq";
475 mac-address = [00 00 00 00 00 00];
476 snps,multicast-filter-bins = <256>;
477 snps,perfect-filter-entries = <128>;
478 tx-fifo-depth = <4096>;
479 rx-fifo-depth = <16384>;
481 clock-names = "stmmaceth", "ptp_ref";
483 reset-names = "stmmaceth", "ahb";
484 snps,axi-config = <&socfpga_axi_setup>;
489 #address-cells = <1>;
490 #size-cells = <0>;
491 compatible = "snps,dw-apb-gpio";
496 porta: gpio-controller@0 {
497 compatible = "snps,dw-apb-gpio-port";
498 gpio-controller;
499 #gpio-cells = <2>;
500 snps,nr-gpios = <29>;
502 interrupt-controller;
503 #interrupt-cells = <2>;
509 #address-cells = <1>;
510 #size-cells = <0>;
511 compatible = "snps,dw-apb-gpio";
516 portb: gpio-controller@0 {
517 compatible = "snps,dw-apb-gpio-port";
518 gpio-controller;
519 #gpio-cells = <2>;
520 snps,nr-gpios = <29>;
522 interrupt-controller;
523 #interrupt-cells = <2>;
529 #address-cells = <1>;
530 #size-cells = <0>;
531 compatible = "snps,dw-apb-gpio";
536 portc: gpio-controller@0 {
537 compatible = "snps,dw-apb-gpio-port";
538 gpio-controller;
539 #gpio-cells = <2>;
540 snps,nr-gpios = <27>;
542 interrupt-controller;
543 #interrupt-cells = <2>;
548 fpga_mgr: fpga-mgr@ffd03000 {
549 compatible = "altr,socfpga-a10-fpga-mgr";
554 reset-names = "fpgamgr";
558 #address-cells = <1>;
559 #size-cells = <0>;
560 compatible = "snps,designware-i2c";
569 #address-cells = <1>;
570 #size-cells = <0>;
571 compatible = "snps,designware-i2c";
580 #address-cells = <1>;
581 #size-cells = <0>;
582 compatible = "snps,designware-i2c";
591 #address-cells = <1>;
592 #size-cells = <0>;
593 compatible = "snps,designware-i2c";
602 #address-cells = <1>;
603 #size-cells = <0>;
604 compatible = "snps,designware-i2c";
613 compatible = "snps,dw-apb-ssi";
614 #address-cells = <1>;
615 #size-cells = <0>;
618 num-cs = <4>;
622 reset-names = "spi";
627 compatible = "snps,dw-apb-ssi";
628 #address-cells = <1>;
629 #size-cells = <0>;
632 num-cs = <4>;
634 tx-dma-channel = <&pdma 16>;
635 rx-dma-channel = <&pdma 17>;
638 reset-names = "spi";
643 compatible = "altr,sdr-ctl", "syscon";
647 L2: cache-controller@fffff000 {
648 compatible = "arm,pl310-cache";
651 cache-unified;
652 cache-level = <2>;
653 prefetch-data = <1>;
654 prefetch-instr = <1>;
655 arm,shared-override;
659 #address-cells = <1>;
660 #size-cells = <0>;
661 compatible = "altr,socfpga-dw-mshc";
664 fifo-depth = <0x400>;
666 clock-names = "biu", "ciu";
668 altr,sysmgr-syscon = <&sysmgr 0x28 4>;
672 nand: nand-controller@ffb90000 {
673 #address-cells = <1>;
674 #size-cells = <0>;
675 compatible = "altr,socfpga-denali-nand";
678 reg-names = "nand_data", "denali_reg";
681 clock-names = "nand", "nand_x", "ecc";
687 compatible = "mmio-sram";
692 compatible = "altr,socfpga-a10-ecc-manager";
693 altr,sysmgr-syscon = <&sysmgr>;
694 #address-cells = <1>;
695 #size-cells = <1>;
698 interrupt-controller;
699 #interrupt-cells = <2>;
703 compatible = "altr,sdram-edac-a10";
704 altr,sdr-syscon = <&sdr>;
709 l2-ecc@ffd06010 {
710 compatible = "altr,socfpga-a10-l2-ecc";
716 ocram-ecc@ff8c3000 {
717 compatible = "altr,socfpga-a10-ocram-ecc";
723 emac0-rx-ecc@ff8c0800 {
724 compatible = "altr,socfpga-eth-mac-ecc";
726 altr,ecc-parent = <&gmac0>;
731 emac0-tx-ecc@ff8c0c00 {
732 compatible = "altr,socfpga-eth-mac-ecc";
734 altr,ecc-parent = <&gmac0>;
739 sdmmca-ecc@ff8c2c00 {
740 compatible = "altr,socfpga-sdmmc-ecc";
742 altr,ecc-parent = <&mmc>;
749 dma-ecc@ff8c8000 {
750 compatible = "altr,socfpga-dma-ecc";
752 altr,ecc-parent = <&pdma>;
757 usb0-ecc@ff8c8800 {
758 compatible = "altr,socfpga-usb-ecc";
760 altr,ecc-parent = <&usb0>;
767 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
768 #address-cells = <1>;
769 #size-cells = <0>;
773 cdns,fifo-depth = <128>;
774 cdns,fifo-width = <4>;
775 cdns,trigger-address = <0x00000000>;
778 reset-names = "qspi", "qspi-ocp";
783 #reset-cells = <1>;
784 compatible = "altr,rst-mgr";
786 altr,modrst-offset = <0x20>;
789 scu: snoop-control-unit@ffffc000 {
790 compatible = "arm,cortex-a9-scu";
795 compatible = "altr,sys-mgr", "syscon";
797 cpu1-start-addr = <0xffd06230>;
802 compatible = "arm,cortex-a9-twd-timer";
809 compatible = "snps,dw-apb-timer";
813 clock-names = "timer";
815 reset-names = "timer";
819 compatible = "snps,dw-apb-timer";
823 clock-names = "timer";
825 reset-names = "timer";
829 compatible = "snps,dw-apb-timer";
833 clock-names = "timer";
835 reset-names = "timer";
839 compatible = "snps,dw-apb-timer";
843 clock-names = "timer";
845 reset-names = "timer";
849 compatible = "snps,dw-apb-uart";
852 reg-shift = <2>;
853 reg-io-width = <4>;
860 compatible = "snps,dw-apb-uart";
863 reg-shift = <2>;
864 reg-io-width = <4>;
871 #phy-cells = <0>;
872 compatible = "usb-nop-xceiv";
881 clock-names = "otg";
883 reset-names = "dwc2";
885 phy-names = "usb2-phy";
894 clock-names = "otg";
896 reset-names = "dwc2";
898 phy-names = "usb2-phy";
903 compatible = "snps,dw-wdt";
912 compatible = "snps,dw-wdt";