Lines Matching +full:irq +full:- +full:gpios

1 // SPDX-License-Identifier: ISC
5  * set-up for IXDP425, IXCDP1100, KIXRP435 and IXDP465.
20 		stdout-path = "uart0:115200n8";
28 		compatible = "i2c-gpio";
29 		sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
30 		scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
31 		#address-cells = <1>;
32 		#size-cells = <0>;
36 			 * Philips PCF8582C-2T/03 512byte I2C EEPROM
43 			read-only;
49 			/* Flash memory defined per-variant */
50 			nand-controller@3,0 {
61 				/* Expansion bus set-up */
62 				intel,ixp4xx-eb-t1 = <0>;
63 				intel,ixp4xx-eb-t2 = <0>;
64 				intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase
65 				intel,ixp4xx-eb-t4 = <0>;
66 				intel,ixp4xx-eb-t5 = <0>;
67 				intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
68 				intel,ixp4xx-eb-byte-access-on-halfword = <0>;
69 				intel,ixp4xx-eb-mux-address-and-data = <0>;
70 				intel,ixp4xx-eb-ahb-split-transfers = <0>;
71 				intel,ixp4xx-eb-write-enable = <1>;
72 				intel,ixp4xx-eb-byte-access = <1>;
76 				nand-on-flash-bbt;
77 				nand-ecc-mode = "soft_bch";
78 				nand-ecc-step-size = <512>;
79 				nand-ecc-strength = <4>;
80 				nce-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* NCE */
85 					compatible = "fixed-partitions";
86 					#address-cells = <1>;
87 					#size-cells = <1>;
109 			#interrupt-cells = <1>;
110 			interrupt-map-mask = <0xf800 0 0 7>;
111 			interrupt-map =
113 			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
114 			<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
115 			<0x0800 0 0 3 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
116 			<0x0800 0 0 4 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
118 			<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
119 			<0x1000 0 0 2 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
120 			<0x1000 0 0 3 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
121 			<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
123 			<0x1800 0 0 1 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
124 			<0x1800 0 0 2 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
125 			<0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
126 			<0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
128 			<0x2000 0 0 1 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */
129 			<0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */
130 			<0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */
131 			<0x2000 0 0 4 &gpio0 9  IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */