intel/ixp/intel-ixp42x-gateworks-gw2348.dts

1 // SPDX-License-Identifier: ISC
7 /dts-v1/;
9 #include "intel-ixp42x.dtsi"
10 #include <dt-bindings/input/input.h>
15 	#address-cells = <1>;
16 	#size-cells = <1>;
25 		stdout-path = "uart0:115200n8";
33 		compatible = "gpio-leds";
34 		led-user {
36 			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
37 			default-state = "on";
38 			linux,default-trigger = "heartbeat";
43 		compatible = "i2c-gpio";
44 		sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
45 		scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
46 		#address-cells = <1>;
47 		#size-cells = <0>;
62 			read-only;
69 				compatible = "intel,ixp4xx-flash", "cfi-flash";
70 				bank-width = <2>;
72 				intel,ixp4xx-eb-write-enable = <1>;
77 					compatible = "redboot-fis";
79 					fis-index-block = <0x7f>;
83 				compatible = "intel,ixp4xx-compact-flash";
87 				 * depending on selected PIO mode (0-4).
89 				intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
90 				intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
91 				intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
92 				intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
93 				intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
94 				intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
95 				intel,ixp4xx-eb-byte-access-on-halfword = <1>;
96 				intel,ixp4xx-eb-mux-address-and-data = <0>;
97 				intel,ixp4xx-eb-ahb-split-transfers = <0>;
98 				intel,ixp4xx-eb-write-enable = <1>;
99 				intel,ixp4xx-eb-byte-access = <1>;
102 				interrupt-parent = <&gpio0>;
118 			#interrupt-cells = <1>;
119 			interrupt-map-mask = <0xf800 0 0 7>;
120 			interrupt-map =
146 			queue-rx = <&qmgr 3>;
147 			queue-txready = <&qmgr 20>;
148 			phy-mode = "rgmii";
149 			phy-handle = <&phy0>;
152 				#address-cells = <1>;
153 				#size-cells = <0>;
155 				phy0: ethernet-phy@0 {
159 				phy1: ethernet-phy@1 {
168 			queue-rx = <&qmgr 4>;
169 			queue-txready = <&qmgr 21>;
170 			phy-mode = "rgmii";
171 			phy-handle = <&phy1>;